PIC18F2320-I/SO Microchip Technology Inc., PIC18F2320-I/SO Datasheet - Page 212

• Manufacturer Part Number: PIC18F2320-I/SO
• Description: Microcontroller; 8 KB Flash; 512 RAM; 256 EEPROM; 25 I/O; 28-Pin-SOIC
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2320-I/SO

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SOIC
• Programmable Memory: 8K Bytes
• Ram Size: 512 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2220/2320/4220/4320
18.5.2
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep or any
Idle mode and bit SREN, which is a “don't care” in
Slave mode.
If receive is enabled by setting bit CREN prior to enter-
ing Sleep or any Idle mode, then a word may be
received while in this power managed mode. Once the
word is received, the RSR register will transfer the data
to the RCREG register and if enable bit RCIE bit is set,
the interrupt generated will wake the chip from the
power managed mode. If the global interrupt is
enabled, the program will branch to the interrupt vector.
TABLE 18-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
DS39599C-page 210
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
SPBRG
Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Note 1:
Name
The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
USART SYNCHRONOUS SLAVE
RECEPTION
USART Receive Register
Baud Rate Generator Register
PSPIF
PSPIE
PSPIP
CSRC
SPEN
GIEH
Bit 7
GIE/
(1)
(1)
(1)
PEIE/
ADIE
ADIP
GIEL
ADIF
Bit 6
RX9
TX9
TMR0IE INT0IE
SREN
TXEN
RCIE
RCIP
RCIF
Bit 5
CREN
SYNC
Bit 4
TXIF
TXIE
TXIP
ADDEN
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
—
TMR0IF INT0IF
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
BRGH
FERR
Bit 2
To set up a Synchronous Slave Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
To enable reception, set enable bit CREN.
Flag bit RCIF will be set when reception is
complete. An interrupt will be generated if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
bit CREN.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
OERR
TRMT
Bit 1
RX9D
TX9D
RBIF
Bit 0
 2003 Microchip Technology Inc.
0000 000x 0000 000u
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
POR, BOR
Value on
Value on
all other
Resets