PIC18F2320-I/SO Microchip Technology Inc., PIC18F2320-I/SO Datasheet - Page 249

• Manufacturer Part Number: PIC18F2320-I/SO
• Description: Microcontroller; 8 KB Flash; 512 RAM; 256 EEPROM; 25 I/O; 28-Pin-SOIC
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2320-I/SO

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SOIC
• Programmable Memory: 8K Bytes
• Ram Size: 512 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

23.3
The Two-Speed Start-up feature helps to minimize the
latency period from oscillator start-up to code execution
by allowing the microcontroller to use the INTRC oscil-
lator as a clock source until the primary clock source is
available. It is enabled by setting the IESO bit in
Configuration Register 1H (CONFIG1H<7>).
Two-Speed Start-up is available only if the primary oscil-
lator mode is LP, XT, HS or HSPLL (Crystal-based
modes). Other sources do not require a OST start-up
delay; for these, Two-Speed Start-up is disabled.
When enabled, Resets and wake-ups from Sleep mode
cause the device to configure itself to run from the inter-
nal oscillator block as the clock source, following the
time-out of the Power-up Timer after a POR Reset is
enabled. This allows almost immediate code execution
while the primary oscillator starts and the OST is run-
ning. Once the OST times out, the device automatically
switches to PRI_RUN mode.
Because the OSCCON register is cleared on Reset
events, the INTOSC (or postscaler) clock source is not
initially available after a Reset event; the INTRC clock
is used directly at its base frequency. To use a higher
clock speed on wake-up, the INTOSC or postscaler
clock sources can be selected to provide a higher clock
speed by setting bits IFRC2:IFRC0 immediately after
FIGURE 23-2:
 2003 Microchip Technology Inc.
Note
Multiplexer
CPU Clock
PLL Clock
Peripheral
Program
INTOSC
Counter
Two-Speed Start-up
Output
OSC1
Clock
1: T
OST
Wake from Interrupt Event
= 1024 T
PC
TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL)
OSC
Q1
; T
PLL
T
OST
= 2 ms (approx). These intervals are not shown to scale.
(1)
Q2
PC + 2
OSTS bit Set
T
Q3
PLL (1)
PIC18F2220/2320/4220/4320
Q4
Q1
1
2
Reset. For wake-ups from Sleep, the INTOSC or
postscaler clock sources can be selected by setting
IFRC2:IFRC0 prior to entering Sleep mode.
In all other power managed modes, Two-Speed Start-up
is not used. The device will be clocked by the currently
selected clock source until the primary clock source
becomes available. The setting of the IESO bit is
ignored.
23.3.1
While using the INTRC oscillator in Two-Speed Start-up,
the device still obeys the normal command sequences
for entering power managed modes, including serial
SLEEP instructions (refer to Section 3.1.3 “Multiple
Sleep Commands”). In practice, this means that user
code can change the SCS1:SCS0 bit settings and issue
SLEEP commands before the OST times out. This would
allow an application to briefly wake-up, perform routine
“housekeeping” tasks and return to Sleep before the
device starts to operate from the primary oscillator.
User code can also check if the primary clock source is
currently providing the system clocking by checking the
status of the OSTS bit (OSCCON<3>). If the bit is set,
the primary oscillator is providing the system clock.
Otherwise, the internal oscillator block is providing the
clock during wake-up from Reset or Sleep mode.
Clock Transition
3
4
5
PC + 4
SPECIAL CONSIDERATIONS FOR
USING TWO-SPEED START-UP
6
7
8
Q2
Q3 Q4
Q1
DS39599C-page 247
Q2
PC + 6
Q3 Q4