PIC18F2320-I/SO Microchip Technology Inc., PIC18F2320-I/SO Datasheet - Page 339

• Manufacturer Part Number: PIC18F2320-I/SO
• Description: Microcontroller; 8 KB Flash; 512 RAM; 256 EEPROM; 25 I/O; 28-Pin-SOIC
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2320-I/SO

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SOIC
• Programmable Memory: 8K Bytes
• Ram Size: 512 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

TABLE 26-19: I
 2003 Microchip Technology Inc.
100
101
102
103
90
91
106
107
92
109
110
D102
Note 1:
Param.
No.
2:
T
T
T
T
T
T
T
T
T
T
T
C
Symbol
SU
SU
SU
AA
HIGH
LOW
R
F
HD
HD
BUF
B
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)
of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
A fast mode I
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line,
T
is released.
:
:
:
:
:
STA
DAT
STO
R
STA
DAT
max. + T
Clock High Time
Clock Low Time
SDA and SCL Rise
Time
SDA and SCL Fall
Time
Start Condition Setup
Time
Start Condition Hold
Time
Data Input Hold Time 100 kHz mode
Data Input Setup
Time
Stop Condition Setup
Time
Output Valid from
Clock
Bus Free Time
Bus Capacitive Loading
2
C BUS DATA REQUIREMENTS (SLAVE MODE)
SU
2
:
C bus device can be used in a standard mode I
DAT
Characteristic
= 1000 + 250 = 1250 ns (according to the standard mode I
100 kHz mode
400 kHz mode
SSP module
100 kHz mode
400 kHz mode
SSP module
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
PIC18F2220/2320/4220/4320
20 + 0.1 C
20 + 0.1 C
1.5 T
1.5 T
Min
250
100
4.0
0.6
4.7
1.3
4.7
0.6
4.0
0.6
4.7
0.6
4.7
1.3
—
—
—
—
—
0
0
CY
CY
B
B
2
C bus system but the requirement, T
1000
3500
Max
300
300
300
0.9
400
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
s
s
s
s
s
s
s
s
s
s
s
s
s
2
C bus specification), before the SCL line
PIC18FXX20 must operate at a
minimum of 1.5 MHz
PIC18FXX20 must operate at a
minimum of 10 MHz
PIC18FXX20 must operate at a
minimum of 1.5 MHz
PIC18FXX20 must operate at a
minimum of 10 MHz
C
C
Only relevant for Repeated
Start condition
After this period, the first clock pulse is
generated
(Note 2)
(Note 1)
Time the bus must be free before a
new transmission can start
B
B
is specified to be from 10 to 400 pF
is specified to be from 10 to 400 pF
Conditions
DS39599C-page 337
SU
:
DAT
250 ns,