PIC18F2320-I/SO Microchip Technology Inc., PIC18F2320-I/SO Datasheet - Page 382

• Manufacturer Part Number: PIC18F2320-I/SO
• Description: Microcontroller; 8 KB Flash; 512 RAM; 256 EEPROM; 25 I/O; 28-Pin-SOIC
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2320-I/SO

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SOIC
• Programmable Memory: 8K Bytes
• Ram Size: 512 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2220/2320/4220/4320
Timer0 .............................................................................. 117
Timer1 .............................................................................. 121
Timer2 .............................................................................. 127
Timer3 .............................................................................. 129
Timing Diagrams
DS39599C-page 380
16-bit Mode Timer Reads and Writes ...................... 119
Associated Registers ............................................... 119
Clock Source Edge Select (T0SE Bit) ...................... 119
Clock Source Select (T0CS Bit) ............................... 119
Interrupt .................................................................... 119
Operation ................................................................. 119
Prescaler. See Prescaler, Timer0.
Switching Prescaler Assignment .............................. 119
16-bit Read/Write Mode ........................................... 124
Associated Registers ............................................... 125
Interrupt .................................................................... 124
Operation ................................................................. 122
Oscillator .......................................................... 121, 123
Oscillator Layout Considerations ............................. 123
Overflow Interrupt ..................................................... 121
Resetting, Using a Special Event
Special Event Trigger (CCP) .................................... 136
TMR1H Register ...................................................... 121
TMR1L Register ....................................................... 121
Use as a Real-Time Clock ....................................... 124
Associated Registers ............................................... 128
Operation ................................................................. 127
Postscaler. See Postscaler, Timer2.
PR2 Register .................................................... 127, 138
Prescaler. See Prescaler, Timer2.
SSP Clock Shift ................................................ 127, 128
TMR2 Register ......................................................... 127
TMR2 to PR2 Match Interrupt .................. 127, 128, 138
Associated Registers ............................................... 131
Operation ................................................................. 130
Oscillator .......................................................... 129, 131
Overflow Interrupt ............................................. 129, 131
Resetting, Using a Special Event
TMR3H Register ...................................................... 129
TMR3L Register ....................................................... 129
A/D Conversion ........................................................ 342
Acknowledge Sequence ........................................... 188
Asynchronous Reception ......................................... 205
Asynchronous Transmission .................................... 203
Asynchronous Transmission (Back to Back) ............ 203
Baud Rate Generator with Clock Arbitration ............ 182
BRG Reset Due to SDA Arbitration
Brown-out Reset (BOR) ........................................... 328
Bus Collision During a Repeated
Bus Collision During a Repeated
Bus Collision During a Stop Condition
Bus Collision During a Stop Condition
Bus Collision During Start Condition
Bus Collision During Start Condition
Bus Collision for Transmit and
Trigger Output (CCP) ....................................... 124
Trigger Output (CCP) ....................................... 131
During Start Condition ...................................... 191
Start Condition (Case 1) .................................. 192
Start Condition (Case 2) .................................. 192
(Case 1) ........................................................... 193
(Case 2) ........................................................... 193
(SCL = 0) .......................................................... 191
(SDA Only) ....................................................... 190
Acknowledge .................................................... 189
Capture/Compare/PWM (CCP) ............................... 330
CLKO and I/O .......................................................... 327
Clock Synchronization ............................................. 175
Clock, Instruction Cycle ............................................. 57
Example SPI Master Mode (CKE = 0) ..................... 332
Example SPI Master Mode (CKE = 1) ..................... 333
Example SPI Slave Mode (CKE = 0) ....................... 334
Example SPI Slave Mode (CKE = 1) ....................... 335
External Clock (All Modes except PLL) ................... 325
Fail-Safe Clock Monitor (FSCM) .............................. 249
First Start Bit ............................................................ 183
Full-Bridge PWM Output .......................................... 146
Half-Bridge PWM Output ......................................... 145
I
I
I
I
I
I
I
I
I
Low-Voltage Detect ................................................. 234
Low-Voltage Detect Characteristics ......................... 322
Master SSP I
Master SSP I
Parallel Slave Port (PIC18F4X20) ........................... 331
Parallel Slave Port (PSP) Read ............................... 115
Parallel Slave Port (PSP) Write ............................... 115
PWM Auto-Shutdown (PRSEN = 0,
PWM Auto-Shutdown (PRSEN = 1,
PWM Direction Change ........................................... 148
PWM Direction Change at Near
PWM Output ............................................................ 138
Repeat Start Condition ............................................ 184
Reset, Watchdog Timer (WDT),
Slave Mode General Call Address
Slave Synchronization ............................................. 161
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ......................................... 160
SPI Mode (Slave Mode with CKE = 0) ..................... 162
SPI Mode (Slave Mode with CKE = 1) ..................... 162
Stop Condition Receive or Transmit Mode .............. 188
Synchronous Transmission ..................................... 206
Synchronous Transmission (Through TXEN) .......... 207
Time-out Sequence on POR w/
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
2
2
2
2
2
2
2
2
2
C Bus Data ............................................................ 336
C Bus Start/Stop Bits ............................................ 336
C Master Mode (Transmission,
C Slave Mode (Transmission, 10-bit Address) ...... 173
C Slave Mode (Transmission, 7-bit Address) ........ 171
C Slave Mode with SEN = 0
C Slave Mode with SEN = 0
C Slave Mode with SEN = 1
C Slave Mode with SEN = 1
7 or 10-bit Address) ......................................... 186
(Reception, 10-bit Address) ............................. 172
(Reception, 7-bit Address) ............................... 170
(Reception, 10-bit Address) ............................. 177
(Reception, 7-bit Address) ............................... 176
Auto-Restart Disabled) .................................... 151
Auto-Restart Enabled) ..................................... 151
100% Duty Cycle ............................................. 148
Oscillator Start-up Timer (OST),
Power-up Timer (PWRT) ................................. 328
Sequence (7 or 10-bit Address Mode) ............. 178
V
PLL Enabled (MCLR Tied to V
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
DD
Rise > T
2
2
C Bus Data ........................................ 338
C Bus Start/Stop Bits ........................ 338
PWRT
 2003 Microchip Technology Inc.
DD
) ............................................ 51
, V
DD
DD
DD
): Case 1 ....................... 50
): Case 2 ....................... 50
Rise T
DD
DD
,
PWRT
) ..................... 51
) .............. 50