PIC24F08KA102-E/ML Microchip Technology Inc., PIC24F08KA102-E/ML Datasheet - Page 141

• Manufacturer Part Number: PIC24F08KA102-E/ML
• Description: 8KB FLASH, 1.5KB RAM, 512B EEPROM, 16 MIPS, 24 I/O, 16-BIT PIC24F FAMILY, NANOWAT
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24F08KA102-E/ML

• A/d Inputs: 9 Channel, 10-bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 28-pin QFN
• Programmable Memory: 8K Bytes
• Ram Size: 1.5K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 125 °C
• Timers: 3-16-bit
• Voltage, Range: 1.8-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part

REGISTER 17-1:
© 2009 Microchip Technology Inc.
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ACKDT: Acknowledge Data bit (when operating as I
Value that will be transmitted when the software initiates an Acknowledge sequence.
1 = Sends NACK during Acknowledge
0 = Sends ACK during Acknowledge
ACKEN: Acknowledge Sequence Enable bit
(when operating as I
1 = Initiates Acknowledge sequence on SDA1 and SCL1 pins and transmits ACKDT data bit; hardware
0 = Acknowledge sequence not in progress
RCEN: Receive Enable bit (when operating as I
1 = Enables Receive mode for I
0 = Receive sequence not in progress
PEN: Stop Condition Enable bit (when operating as I
1 = Initiates Stop condition on SDA1 and SCL1 pins; hardware clear at end of master Stop sequence
0 = Stop condition not in progress
RSEN: Repeated Start Condition Enable bit (when operating as I
1 = Initiates Repeated Start condition on SDA1 and SCL1 pins; hardware clear at end of master
0 = Repeated Start condition not in progress
SEN: Start Condition Enable bit (when operating as I
1 = Initiates Start condition on SDA1 and SCL1 pins; hardware clear at end of master Start sequence
0 = Start condition not in progress
clear at end of master Acknowledge sequence
Repeated Start sequence
I2C1CON: I2C1 CONTROL REGISTER (CONTINUED)
2
C master; applicable during master receive)
2
C; hardware clear at end of eighth bit of master receive data byte
Preliminary
PIC24F16KA102 FAMILY
2
C master)
2
2
2
C master; applicable during master receive)
C master)
C master)
2
C master)
DS39927B-page 139