PIC24F08KA102-E/ML Microchip Technology Inc., PIC24F08KA102-E/ML Datasheet - Page 146

• Manufacturer Part Number: PIC24F08KA102-E/ML
• Description: 8KB FLASH, 1.5KB RAM, 512B EEPROM, 16 MIPS, 24 I/O, 16-BIT PIC24F FAMILY, NANOWAT
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24F08KA102-E/ML

• A/d Inputs: 9 Channel, 10-bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 28-pin QFN
• Programmable Memory: 8K Bytes
• Ram Size: 1.5K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 125 °C
• Timers: 3-16-bit
• Voltage, Range: 1.8-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC24F16KA102 FAMILY
18.1
The UART module includes a dedicated 16-bit Baud
Rate Generator (BRG). The UxBRG register controls
the period of a free-running, 16-bit timer. Equation 18-1
provides the formula for computation of the baud rate
with BRGH = 0.
EQUATION 18-1:
Example 18-1 provides the calculation of the baud rate
error for the following conditions:
• F
• Desired Baud Rate = 9600
EXAMPLE 18-1:
DS39927B-page 144
Note 1:
Desired Baud Rate
Solving for UxBRG value:
Calculated Baud Rate = 4000000/(16 (25 + 1))
Error
Note 1:
CY
= 4 MHz
UART Baud Rate Generator (BRG)
UxBRG
UxBRG
UxBRG
Baud Rate =
UxBRG =
Based on F
and PLL are disabled.
Based on F
UART BAUD RATE WITH
BRGH = 0
BAUD RATE ERROR CALCULATION (BRGH = 0)
16 • (UxBRG + 1)
CY
16 • Baud Rate
= F
= ((F
= ((4000000/9600)/16) – 1
= 25
= 9615
= (Calculated Baud Rate – Desired Baud Rate)
= (9615 – 9600)/9600
= 0.16%
CY
= F
Desired Baud Rate
= F
CY
F
F
CY
CY
OSC
CY
/(16 (UxBRG + 1))
OSC
/Desired Baud Rate)/16) – 1
(1)
/2, Doze mode
/2, Doze mode and PLL are disabled.
– 1
Preliminary
The maximum baud rate (BRGH = 0) possible is
F
possible is F
Equation 18-2 provides the formula for computation of
the baud rate with BRGH = 1.
EQUATION 18-2:
The maximum baud rate (BRGH = 1) possible is F
(for UxBRG = 0) and the minimum baud rate possible
is F
Writing a new value to the UxBRG register causes the
BRG timer to be reset (cleared). This ensures the BRG
does not wait for a timer overflow before generating the
new baud rate.
CY
Note 1:
CY
/16 (for UxBRG = 0) and the minimum baud rate
/(4 * 65536).
Baud Rate =
UxBRG =
CY
Based on F
and PLL are disabled.
/(16 * 65536).
(1)
UART BAUD RATE WITH
BRGH = 1
© 2009 Microchip Technology Inc.
4 • (UxBRG + 1)
CY
4 • Baud Rate
= F
F
F
OSC
CY
CY
(1)
/2, Doze mode
– 1
CY
/4