PIC24F08KA102-E/ML Microchip Technology Inc., PIC24F08KA102-E/ML Datasheet - Page 145

• Manufacturer Part Number: PIC24F08KA102-E/ML
• Description: 8KB FLASH, 1.5KB RAM, 512B EEPROM, 16 MIPS, 24 I/O, 16-BIT PIC24F FAMILY, NANOWAT
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24F08KA102-E/ML

• A/d Inputs: 9 Channel, 10-bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 28-pin QFN
• Programmable Memory: 8K Bytes
• Ram Size: 1.5K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 125 °C
• Timers: 3-16-bit
• Voltage, Range: 1.8-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part

18.0
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules avail-
able in this PIC24F device family. The UART is a
full-duplex asynchronous system that can communicate
with peripheral devices, such as personal computers,
LIN, RS-232 and RS-485 interfaces. This module also
supports a hardware flow control option with the UxCTS
and UxRTS pins, and also includes an IrDA
and decoder.
The primary features of the UART module are:
• Full-Duplex, 8-Bit or 9-Bit Data Transmission
• Even, Odd or No Parity Options (for 8-bit data)
• One or Two Stop bits
• Hardware Flow Control Option with UxCTS and
FIGURE 18-1:
© 2009 Microchip Technology Inc.
Note:
through the UxTX and UxRX pins
UxRTS pins
UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on the
Universal
Transmitter, refer to the “PIC24F Family
Reference Manual”, Section 21. “UART”
(DS39708).
UART SIMPLIFIED BLOCK DIAGRAM
Asynchronous
Hardware Flow Control
Baud Rate Generator
UARTx Transmitter
UARTx Receiver
IrDA
®
®
Receiver
encoder
Preliminary
PIC24F16KA102 FAMILY
• Fully Integrated Baud Rate Generator (IBRG) with
• Baud Rates Ranging from 1 Mbps to 15 bps at
• 4-Deep, First-In-First-Out (FIFO) Transmit Data
• 4-Deep FIFO Receive Data Buffer
• Parity, Framing and Buffer Overrun Error
• Support for 9-Bit mode with Address Detect (9
• Transmit and Receive Interrupts
• Loopback mode for Diagnostic Support
• Support for Sync and Break Characters
• Supports Automatic Baud Rate Detection
• IrDA Encoder and Decoder Logic
• 16x Baud Clock Output for IrDA Support
A simplified block diagram of the UART is displayed in
Figure 18-1. The UART module consists of these
important hardware elements:
• Baud Rate Generator
• Asynchronous Transmitter
• Asynchronous Receiver
16-Bit Prescaler
16 MIPS
Buffer
Detection
bit = 1)
UxBCLK
UxRTS
UxCTS
UxRX
UxTX
DS39927B-page 143
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