PIC24F08KA102-E/ML Microchip Technology Inc., PIC24F08KA102-E/ML Datasheet - Page 189

• Manufacturer Part Number: PIC24F08KA102-E/ML
• Description: 8KB FLASH, 1.5KB RAM, 512B EEPROM, 16 MIPS, 24 I/O, 16-BIT PIC24F FAMILY, NANOWAT
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24F08KA102-E/ML

• A/d Inputs: 9 Channel, 10-bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 28-pin QFN
• Programmable Memory: 8K Bytes
• Ram Size: 1.5K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 125 °C
• Timers: 3-16-bit
• Voltage, Range: 1.8-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part

REGISTER 25-1:
© 2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 10
bit 10
bit 9
bit 8
bit 7
bit 6-5
bit 4
EDG2POL
CTMUEN
R/W-0
R/W-0
CTMUEN: CTMU Enable bit
1 = Module is enabled
0 = Module is disabled
Unimplemented: Read as ‘0’
CTMUSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
TGEN: Time Generation Enable bit
1 = Enables edge delay generation
0 = Disables edge delay generation
EDGEN: Edge Enable bit
1 = Edges are not blocked
0 = Edges are blocked
EDGSEQEN: Edge Sequence Enable bit
1 = Edge 1 event must occur before Edge 2 event can occur
0 = No edge sequence is needed
IDISSEN: Analog Current Source Control bit
1 = Analog current source output is grounded
0 = Analog current source output is not grounded
CTTRIG: Trigger Control bit
1 = Trigger output is enabled
0 = Trigger output is disabled
EDG2POL: Edge 2 Polarity Select bit
1 = Edge 2 programmed for a positive edge response
0 = Edge 2 programmed for a negative edge response
EDG2SEL<1:0>: Edge 2 Source Select bits
11 = CTED1 pin
10 = CTED2 pin
01 = OC1 module
00 = Timer1 module
EDG1POL: Edge 1 Polarity Select bit
1 = Edge 1 programmed for a positive edge response
0 = Edge 1 programmed for a negative edge response
EDG2SEL1
R/W-0
U-0
—
CTMUCON: CTMU CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
CTMUSIDL
EDG2SEL0
R/W-0
R/W-0
EDG1POL
R/W-0
TGEN
R/W-0
Preliminary
PIC24F16KA102 FAMILY
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
EDG1SEL1
EDGEN
R/W-0
R/W-0
EDGSEQEN
EDG1SEL0
R/W-0
R/W-0
x = Bit is unknown
EDG2STAT
IDISSEN
R/W-0
R/W-0
DS39927B-page 187
EDG1STAT
CTTRIG
R/W-0
R/W-0
bit 8
bit 0