PIC24F08KA102-E/ML Microchip Technology Inc., PIC24F08KA102-E/ML Datasheet - Page 61

• Manufacturer Part Number: PIC24F08KA102-E/ML
• Description: 8KB FLASH, 1.5KB RAM, 512B EEPROM, 16 MIPS, 24 I/O, 16-BIT PIC24F FAMILY, NANOWAT
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24F08KA102-E/ML

• A/d Inputs: 9 Channel, 10-bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 28-pin QFN
• Programmable Memory: 8K Bytes
• Ram Size: 1.5K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 125 °C
• Timers: 3-16-bit
• Voltage, Range: 1.8-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part

REGISTER 7-1:
TABLE 7-1:
7.1
If clock switching is enabled, the system clock source at
device Reset is chosen as shown in Table 7-2. If clock
switching is disabled, the system clock source is always
selected according to the oscillator Configuration bits.
Refer to Section 8.0 “Oscillator Configuration” for
further details.
© 2009 Microchip Technology Inc.
bit 1
bit 0
Note 1:
TRAPR (RCON<15>)
IOPUWR (RCON<14>)
CM (RCON<9>)
EXTR (RCON<7>)
SWR (RCON<6>)
WDTO (RCON<4>)
SLEEP (RCON<3>)
IDLE (RCON<2>)
BOR (RCON<1>)
POR (RCON<0>)
DPSLP (RCON<10>)
Note:
2:
Clock Source Selection at Reset
All Reset flag bits may be set or cleared by the user software.
Flag Bit
All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
BOR: Brown-out Reset Flag bit
1 = A Brown-out Reset has occurred (the BOR is also set after a POR)
0 = A Brown-out Reset has not occurred
POR: Power-on Reset Flag bit
1 = A Power-up Reset has occurred
0 = A Power-up Reset has not occurred
RESET FLAG BIT OPERATION
RCON: RESET CONTROL REGISTER
Trap Conflict Event
Illegal Opcode or Uninitialized W Register Access
Configuration Mismatch Reset
MCLR Reset
RESET Instruction
WDT Time-out
PWRSAV #SLEEP Instruction
PWRSAV #IDLE Instruction
POR, BOR
POR
PWRSAV #SLEEP instruction with DSCON <DSEN> set
Preliminary
Setting Event
PIC24F16KA102 FAMILY
TABLE 7-2:
Reset Type
(1)
WDTO
MCLR
SWR
POR
BOR
(CONTINUED)
FNOSC Configuration bits
(FNOSC<10:8>)
COSC Control bits
(OSCCON<14:12>)
OSCILLATOR SELECTION vs.
TYPE OF RESET (CLOCK
SWITCHING ENABLED)
Clock Source Determinant
PWRSAV Instruction, POR
Clearing Event
DS39927B-page 59
POR
POR
POR
POR
POR
POR
POR
POR
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