PIC24F08KA102-E/ML Microchip Technology Inc., PIC24F08KA102-E/ML Datasheet - Page 59

• Manufacturer Part Number: PIC24F08KA102-E/ML
• Description: 8KB FLASH, 1.5KB RAM, 512B EEPROM, 16 MIPS, 24 I/O, 16-BIT PIC24F FAMILY, NANOWAT
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24F08KA102-E/ML

• A/d Inputs: 9 Channel, 10-bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 28-pin QFN
• Programmable Memory: 8K Bytes
• Ram Size: 1.5K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 125 °C
• Timers: 3-16-bit
• Voltage, Range: 1.8-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part

7.0
The Reset module combines all Reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
• POR: Power-on Reset
• MCLR: Pin Reset
• SWR: RESET Instruction
• WDTR: Watchdog Timer Reset
• BOR: Brown-out Reset
• Low-Power BOR/Deep Sleep BOR
• TRAPR: Trap Conflict Reset
• IOPUWR: Illegal Opcode Reset
• UWR: Uninitialized W Register Reset
Figure 7-1 displays a simplified block diagram of the
Reset module.
FIGURE 7-1:
© 2009 Microchip Technology Inc.
Note:
RCON<SBOREN>
RESETS
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on Resets,
refer to the “PIC24F Family Reference
Manual”,
Programmable Brown-out Reset”.
SLEEP
0
1
BOREN<1:0>
RESET SYSTEM BLOCK DIAGRAM
Section
00
01
10
11
MCLR
V
40.
DD
Uninitialized W Register
“Reset
Illegal Opcode
Trap Conflict
Sleep or Idle
Brown-out
V
RESET
Instruction
Module
DD
Detect
WDT
Reset
Rise
with
Preliminary
PIC24F16KA102 FAMILY
Glitch Filter
Any active source of Reset will make the SYSRST
signal active. Many registers associated with the CPU
and peripherals are forced to a known Reset state.
Most registers are unaffected by a Reset; their status is
unknown on Power-on Reset (POR) and unchanged by
all other Resets.
All types of device Reset will set a corresponding status
bit in the RCON register to indicate the type of Reset
(see Register 7-1). A POR will clear all bits except for
the BOR and POR bits (RCON<1:0>) which are set.
The user may set or clear any bit at any time during
code execution. The RCON bits only serve as status
bits. Setting a particular Reset status bit in software will
not cause a device Reset to occur.
The RCON register also has other bits associated with
the Watchdog Timer (WDT) and device power-saving
states. The function of these bits is discussed in other
sections of this manual.
Note:
Note:
POR
BOR
Refer to the specific peripheral or CPU
section of this manual for register Reset
states.
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
DS39927B-page 57
SYSRST