PIC24F08KA102-E/ML Microchip Technology Inc., PIC24F08KA102-E/ML Datasheet - Page 54

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PIC24F08KA102-E/ML

Manufacturer Part Number
PIC24F08KA102-E/ML
Description
8KB FLASH, 1.5KB RAM, 512B EEPROM, 16 MIPS, 24 I/O, 16-BIT PIC24F FAMILY, NANOWAT
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC24F08KA102-E/ML

A/d Inputs
9 Channel, 10-bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
0 Bytes
Input Output
24
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
16
Package Type
28-pin QFN
Programmable Memory
8K Bytes
Ram Size
1.5K Bytes
Speed
32 MHz
Temperature Range
–40 to 125 °C
Timers
3-16-bit
Voltage, Range
1.8-3.6 V
Lead Free Status / Rohs Status
RoHS Compliant part
PIC24F16KA102 FAMILY
REGISTER 6-1:
DS39927B-page 52
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11-7
bit 6
bit 5-0
R/S-0, HC
WR
U-0
WR: Write Control bit (program or erase)
1 = Initiates a data EEPROM erase or write cycle (can be set but not cleared in software)
0 = Write cycle is complete (cleared automatically by hardware)
WREN: Write Enable bit (erase or program)
1 = Enable an erase or program operation
0 = No operation allowed (device clears this bit on completion of the write/erase operation)
WRERR: Flash Error Flag bit
1 = A write operation is prematurely terminated (any MCLR or WDT Reset during programming
0 = The write operation completed successfully
PGMONLY: Program Only Enable bit
1 = Write operation is executed without erasing target address(es) first
0 = Automatic erase-before-write: write operations are preceded automatically by an erase of target
Unimplemented: Read as ‘0’
ERASE: Erase Operation Select bit
1 = Perform an erase operation when WR is set
0 = Perform a write operation when WR is set
NVMOP<5:0>: Programming Operation Command Byte bits
Erase Operations (when ERASE bit is ‘1’):
011010 = Erase 8 words
011001 = Erase 4 words
011000 = Erase 1 word
0100xx = Erase entire data EEPROM
Programming Operations (when ERASE bit is ‘0’):
001xx = Write 1 word
ERASE
WREN
R/W-0
R/W-0
operation)
address(es)
NVMCON: NONVOLATILE MEMORY CONTROL REGISTER
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
NVMOP5
WRERR
R/W-0
R/W-0
PGMONLY
NVMOP4
R/W-0
R/W-0
Preliminary
S = Settable bit
‘0’ = Bit is cleared
NVMOP3
R/W-0
U-0
NVMOP2
R/W-0
U-0
HC = Hardware Clearable bit
x = Bit is unknown
© 2009 Microchip Technology Inc.
NVMOP1
R/W-0
U-0
NVMOP0
R/W-0
U-0
bit 8
bit 0

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