VSC8641XKO Vitesse Semiconductor Corp, VSC8641XKO Datasheet - Page 10

• Manufacturer Part Number: VSC8641XKO
• Description: IC PHY 10/100/1000 100-LQFP
• Manufacturer: Vitesse Semiconductor Corp
• Type: PHY Transceiverr

Specifications of VSC8641XKO

• Number Of Drivers/receivers: 1/1
• Protocol: Gigabit Ethernet
• Voltage - Supply: 2.5V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Case: TQFP
• Dc: 07+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 907-1031

Revision History
Revision 4.3
Revision 4.2
Revision 4.3
August 2009
This section describes the changes that were implemented in this document. The
changes are listed by revision, starting with the most current publication.
Revision 4.3 of this datasheet was published in August 2009. The following is a
summary of the changes implemented in the datasheet:
•
•
Revision 4.2 of this datasheet was published in May 2008. The following is a summary
of the changes implemented in the datasheet:
•
•
•
VSC8641XJF device information was added.
Three design considerations were added:
Voltage Overshoot When Using On-Chip Switching Regulator The device’s
on-chip switching regulator generates notable voltage overshoot, which may lead to
device performance issues such as CRC errors, jitter, or both.
Long Link-Up Times Caused by Noise on the Twisted Pair
Interface
auto-negotiation when there is signal noise coming from the link partner. However,
on rare occasions when the VSC8641 device uses the same cable as the link
partner, the link-up time can be significantly increased for successful
auto-negotiation.
High VDD33 and Low VDDIOMAC Supply
allowed 3.3 V supply and VDDIOMAC is set to the minimum allowed 3.3 V supply,
the VSC8641 device can experience performance issues.
For more information about the design considerations and their workarounds, see
“Design Considerations,”
The delay setting for register 23, bit 8 was corrected from 2 ns to 1.7 ns.
Additionally, the RGMII clock skew function was updated to clarify that CMODE pin
2, bit 1, and 0 will set both register 23, bit 8 and register 28E, bits 15:12.
A note was added to the serial management interface pin descriptions to clarify that
the NRESET pin is referenced to VDD33. Additionally, referenced VDD33 pins
OSCEN, PLLMODE, REG_EN, and REF_CLK were added to the pin identifications.
Four design guidelines were added to the design considerations:
Default 10Base-T Settings are Marginal and Cause MAU Test Failure The
default settings are marginal for PHY silicon and magnetic module variations and
may cause the output 10Base-T signal to violate the IEEE waveform template.
On-Chip Pull-up Resistor Violation
Normally, the VSC8641 device successfully links during
page 118.
An on-chip pull-up resistor included on the
If VDD33 is set to the maximum
VSC8641 Datasheet
Revision History
Page 10