VSC8641XKO Vitesse Semiconductor Corp, VSC8641XKO Datasheet - Page 42

• Manufacturer Part Number: VSC8641XKO
• Description: IC PHY 10/100/1000 100-LQFP
• Manufacturer: Vitesse Semiconductor Corp
• Type: PHY Transceiverr

Specifications of VSC8641XKO

• Number Of Drivers/receivers: 1/1
• Protocol: Gigabit Ethernet
• Voltage - Supply: 2.5V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Case: TQFP
• Dc: 07+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 907-1031

Table 7.
4.2.1
Table 8.
Revision 4.3
August 2009
Main Registers (continued)
Mode Control
The device register at memory address 0.00.15:0 controls several aspects of VSC8641
functionality. The following table lists the available bit settings in this register and what
they control.
Mode Control, Address 0 (0x00)
Bit
15
14
13, 6
12
Register Address
Name
Software reset
Loopback
Forced speed
selection
Auto-negotiation
enable
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Register Name
Bypass control
Receive error counter
False carrier sense counter
Disconnect counter
Extended control and status
Extended PHY control 1
Extended PHY control 2
Interrupt mask
Interrupt status
LED control
Auxiliary control and status
Delay skew status
Reserved
Extended register page access
Access
R/W
R/W
R/W
R/W
serial management interface (SMI) registers
to their default state, except for sticky and
super sticky bits.
1 = Reset asserted.
0 = Reset de-asserted.
You must wait 4 µs after setting this bit to
initiate another SMI register access.
0 = Loopback disabled.
When loop back is enabled, the device
functions at the current speed setting and
with the current duplex mode setting (bit 8
of this register).
00 = 10 Mbps.
01 = 100 Mbps.
10 = 1000 Mbps.
11 = Reserved.
1 = Auto-negotiation enabled.
0 = Auto-negotiation disabled.
Description
This is a self-clearing bit that restores all
1 = Loopback enabled.
LSB = bit 13, MSB = bit 6.
VSC8641 Datasheet
Configuration
Default
Page 42
10
0
0
1