WJLXT972ALC.A4 Intel, WJLXT972ALC.A4 Datasheet - Page 24

• Manufacturer Part Number: WJLXT972ALC.A4
• Description: IC TRANS 3.3V ETHERNET 64-LQFP
• Manufacturer: Intel
• Type: Transceiverr

Specifications of WJLXT972ALC.A4

• Number Of Drivers/receivers: 1/1
• Protocol: IEEE 802
• Voltage - Supply: 3.14 V ~ 3.45 V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 857341

LXT972M PHY
Datasheet
302875, Revision 5.3
31 October 2007
5.2.3.1.1
Table 13
5.2.3.1.2
Figure 3
Figure 4
Cortina Systems
The LXT972M PHY supports the IEEE 802.3 MII Management Interface also known as
the Management Data Input/Output (MDIO) Interface. This interface allows upper-layer
devices to monitor and control the state of the LXT972M PHY. The MDIO interface
consists of a physical connection, a specific protocol that runs across the connection, and
an internal set of addressable registers.
Some registers are required and their functions are defined by the IEEE 802.3 standard.
The LXT972M PHY also supports additional registers for expanded functionality. The
LXT972M PHY supports multiple internal registers, each of which is 16 bits wide. Specific
register bits are referenced using an “X.Y” notation, where X is the register number (0-31)
and Y is the bit number (0-15).
MDIO Addressing
The MDIO addressing protocol allows a controller to communicate with multiple PHYs.
Pins ADDR[1:0] determine the PHY device address that is selected (see
PHY Device Address Selections
MDIO Frame Structure
The physical interface consists of a data line (MDIO) and clock line (MDC). The frame
structure is shown in
MDIO Interface timing is given in
Management Interface Read Frame Structure
Management Interface Write Frame Structure
®
MDIO
(Read)
(Write)
MDC
LXT972M Single-Port 10/100 Mbps PHY Transceiver
MDIO
(Pin 11)
MDC
High Z
ADDR1
Idle
0
0
1
1
Preamble
32 "1"s
Preamble
32 "1"s
0
0
(Pin 10)
ST
ADDR0
ST
1
1
0
1
0
1
Figure 3
1
0
Op Code
Op Code
1
0
Write
PHY Device
and
A4
A4
Selected
Address
PHY Address
PHY Address
Section 7.0, Electrical Specifications.
28
29
0
1
Figure 4
A3
A3
A0
A0
Write
R4
R4
(Read and Write).
Register Address
Register Address
R3
R3
R0
R0
1
Z
Around
Around
Turn
Turn
0
0
D15
D15
5.2 Network Media / Protocol
D15
D14
D14
Data
Read
D14
Data
D1
D1
D1
Table
D0
D0
13).
Idle
B3490-01
Idle
B3489-01
Support
Page 24