WJLXT972ALC.A4 Intel, WJLXT972ALC.A4 Datasheet - Page 27

• Manufacturer Part Number: WJLXT972ALC.A4
• Description: IC TRANS 3.3V ETHERNET 64-LQFP
• Manufacturer: Intel
• Type: Transceiverr

Specifications of WJLXT972ALC.A4

• Number Of Drivers/receivers: 1/1
• Protocol: IEEE 802
• Voltage - Supply: 3.14 V ~ 3.45 V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 857341

LXT972M PHY
Datasheet
302875, Revision 5.3
31 October 2007
5.4.1
5.4.2
5.4.2.1
5.4.3
Cortina Systems
MDIO Control Mode and Hardware Control Mode
In the MDIO Control mode, the LXT972M PHY reads the Hardware Control Interface pins
to set the initial (default) values of the MDIO registers. Once the initial values are set, bit
control reverts to the MDIO interface.
The following modes are available using either Hardware Control or MDIO control:
On power-up or hardware reset, the LXT972M PHY reads the Hardware Control Interface
pins and sets the MDIO registers accordingly.
The following modes are available using the Hardware Control:
When the network link is forced to a specific configuration, the LXT972M PHY
immediately begins operating the network interface as commanded. When auto-
negotiation is enabled, the LXT972M PHY begins the auto-negotiation/parallel-detection
operation.
Reduced-Power Modes
This section discusses the LXT972M PHY reduced-power modes.
Software Power Down
Software power-down control is provided by register bit 0.11 in the Control Register.
During soft power-down, the following conditions are true:
Reset
The LXT972M PHY provides both hardware and software resets, each of which manage
differently the configuration control of auto-negotiation, speed, and duplex-mode
selection.
For a software reset, register bit 0.15 = 1. For register bit definitions used for software
reset, see
®
• Force network link operation to:
• Allow auto-negotiation/parallel-detection
• Auto-negotiation-enabled advertising, either:
• Device ID enable
• Link Hold-off
• The network port is shut down.
• The MDIO registers remain accessible.
• During a software reset, bit settings in
LXT972M Single-Port 10/100 Mbps PHY Transceiver
— 100BASE-TX, Full-Duplex
— 100BASE-TX, Half-Duplex
— 10BASE-T, Full-Duplex
— 10BASE-T, Half-Duplex
— 10/100 BASE-T Full/Half Duplex
— 10/100 BASE-T Half Duplex
Register - Address 4, Hex 4, on page 68
configuration pins. Instead, the bit settings revert to the values that were read in
Table 40, Control Register - Address 0, Hex 0, on page
Table 44, Auto-Negotiation Advertisement
are not re-read from the LXT972M PHY
65.
5.4 Initialization
Page 27