WJLXT972ALC.A4 Intel, WJLXT972ALC.A4 Datasheet - Page 75

• Manufacturer Part Number: WJLXT972ALC.A4
• Description: IC TRANS 3.3V ETHERNET 64-LQFP
• Manufacturer: Intel
• Type: Transceiverr

Specifications of WJLXT972ALC.A4

• Number Of Drivers/receivers: 1/1
• Protocol: IEEE 802
• Voltage - Supply: 3.14 V ~ 3.45 V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 857341

LXT972M PHY
Datasheet
302875, Revision 5.3
31 October 2007
Table 52
Table 53
Cortina Systems
Interrupt Enable Register - Address 18, Hex 12
Status Change Register - Address 19, Hex 13 (Sheet 1 of 2)
®
18.
15:9
18.8
18.7
18.6
18.5
18.4
18.3
18.2
18.1
18.0
1. R/W = Read /Write
19.15:9
19.8
19.7
19.6
19.5
1. R/W = Read/Write, RO = Read Only, SC = Self Clearing.
LXT972M Single-Port 10/100 Mbps PHY Transceiver
Bit
Bit
Reserved
Reserved
ANMSK
SPEEDMSK
DUPLEXMSK
LINKMSK
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ANDONE
SPEEDCHG
DUPLEXCHG
Name
Name
Auto-negotiation Status
0 = Auto-negotiation has not completed.
1 = Auto-negotiation has completed.
Speed Change Status
0 = A Speed Change has not occurred since last
1 = A Speed Change has occurred since last reading
Duplex Change Status
0 = A Duplex Change has not occurred since last
1 = A Duplex Change has occurred since last
Ignore on Read.
Ignore on Read.
Write as ‘0’. Ignore on Read.
Write as ‘0’. Ignore on Read.
Mask for Auto Negotiate Complete
0 = Do not allow event to cause interrupt.
1 = Enable event to cause interrupt.
Mask for Speed Interrupt
0 = Do not allow event to cause interrupt.
1 = Enable event to cause interrupt.
Mask for Duplex Interrupt
0 = Do not allow event to cause interrupt.
1 = Enable event to cause interrupt.
Mask for Link Status Interrupt
0 = Do not allow event to cause interrupt.
1 = Enable event to cause interrupt.
Write as ‘0’. Ignore on Read.
Write as ‘0’. Ignore on Read.
Write as ‘0’. Ignore on Read.
Question 1
Write as ‘0’. Ignore on Read.
reading this register.
this register.
reading this register.
reading this register.
Description
Description
Product-Specific Registers
9.0 Register Definitions -
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO/
RO/
RO/
RO
RO
SC
SC
SC
1
1
Default
Default
N/A
Page 75
N/A
N/A
0
0
0
0
0
0
0
0
0
0
0
0