WJLXT972ALC.A4 Intel, WJLXT972ALC.A4 Datasheet - Page 5

• Manufacturer Part Number: WJLXT972ALC.A4
• Description: IC TRANS 3.3V ETHERNET 64-LQFP
• Manufacturer: Intel
• Type: Transceiverr

Specifications of WJLXT972ALC.A4

• Number Of Drivers/receivers: 1/1
• Protocol: IEEE 802
• Voltage - Supply: 3.14 V ~ 3.45 V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 857341

LXT972M PHY
Datasheet
302875, Revision 5.3
31 October 2007
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Cortina Systems
Block Diagram ...............................................................................................................................11
48-Pin LQFP Package: Pin Assignments ......................................................................................13
Management Interface Read Frame Structure .............................................................................24
Management Interface Write Frame Structure .............................................................................24
Initialization Sequence...................................................................................................................26
Clocking for 10BASE-T .................................................................................................................31
Clocking for 100BASE-X ..............................................................................................................32
Clocking for Link Down Clock Transition ...................................................................................... 32
Loopback Paths .............................................................................................................................34
100BASE-X Frame Format ...........................................................................................................35
100BASE-TX Data Path ...............................................................................................................36
100BASE-TX Reception with No Errors .......................................................................................36
100BASE-TX Reception with Invalid Symbol ...............................................................................37
100BASE-TX Transmission with No Errors ..................................................................................37
100BASE-TX Transmission with Collision ....................................................................................37
Protocol Sublayers .......................................................................................................................38
LED Pulse Stretching ...................................................................................................................45
Typical Twisted-Pair Interface - Switch .........................................................................................48
Typical Twisted-Pair Interface - NIC ..............................................................................................49
Typical Media Independent Interface ............................................................................................50
100BASE-TX Receive Timing .......................................................................................................55
100BASE-TX Transmit Timing ......................................................................................................56
10BASE-T Receive Timing ............................................................................................................57
10BASE-T Transmit Timing ..........................................................................................................58
10BASE-T Jabber and Unjabber Timing ......................................................................................59
10BASE-T SQE (Heartbeat) Timing .............................................................................................59
Auto-Negotiation and Fast Link Pulse Timing ...............................................................................60
Fast Link Pulse Timing ..................................................................................................................60
MDIO Input Timing ........................................................................................................................61
MDIO Output Timing......................................................................................................................61
Power-Up Timing...........................................................................................................................62
RESET_L Pulse Width and Recovery Timing ...............................................................................62
PHY Identifier Bit Mapping ...........................................................................................................67
LQFP Package Specifications .......................................................................................................80
Link Establishment Overview .......................................................................................................29
®
LXT972M Single-Port 10/100 Mbps PHY Transceiver
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