WJLXT972ALC.A4 Intel, WJLXT972ALC.A4 Datasheet - Page 42

• Manufacturer Part Number: WJLXT972ALC.A4
• Description: IC TRANS 3.3V ETHERNET 64-LQFP
• Manufacturer: Intel
• Type: Transceiverr

Specifications of WJLXT972ALC.A4

• Number Of Drivers/receivers: 1/1
• Protocol: IEEE 802
• Voltage - Supply: 3.14 V ~ 3.45 V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 857341

LXT972M PHY
Datasheet
302875, Revision 5.3
31 October 2007
5.7.3.3.4
5.8
5.8.1
5.8.2
5.8.3
5.8.4
Cortina Systems
Programmable Slew Rate Control
The LXT972M PHY device supports a programmable slew-rate mechanism whereby one
of four pre-selected slew rates can be used. (For details, see
Register - Address 30, Hex 1E, on page
designer to optimize the output waveform to match the characteristics of the magnetics.
10 Mbps Operation
The LXT972M PHY operates as a standard 10BASE-T PHY and LXT972M PHY supports
standard 10 Mbps functions. During 10BASE-T operation, the LXT972M PHY transmits
and receives Xilinks* Manchester-encoded data across the network link. When the MAC
is not actively transmitting data, the LXT972M PHY drives link pulses onto the line.
In 10BASE-T mode, the polynomial scrambler/de-scrambler is inactive. Manchester-
encoded signals received from the network are decoded by the LXT972M PHY and sent
across the MII to the MAC.
10BASE-T Preamble Handling
The LXT972M PHY offers two options for preamble handling, selected by register bit 16.5.
10BASE-T Carrier Sense
For 10BASE-T links, CRS assertion is based on reception of valid preamble, and CRS de-
assertion is based on reception of an end-of-frame (EOF) marker. register bit 16.7 allows
CRS de-assertion to be synchronized with RX_DV de-assertion. For details, see
Configuration Register - Address 16, Hex 10, on page
10BASE-T Dribble Bits
The LXT972M PHY handles dribble bits in all modes. If one to four dribble bits are
received, the nibble is passed across the MII, padded with ones if necessary. If five to
seven dribble bits are received, the second nibble is not sent to the MII bus.
10BASE-T Link Integrity Test
In 10BASE-T mode, the LXT972M PHY always transmits link pulses.
®
• In 10BASE-T mode when register bit 16.5 = 0, the LXT972M PHY strips the entire
• In 10BASE-T mode when register bit 16.5 = 1, the LXT972M PHY passes the
• If the Link Integrity Test function is enabled (the normal configuration), the LXT972M
LXT972M Single-Port 10/100 Mbps PHY Transceiver
preamble off of received packets. CRS is asserted coincident with the start of the
preamble. RX_DV is held Low for the duration of the preamble. When RX_DV is
asserted, the very first two nibbles driven by the LXT972M PHY are the SFD “5D” hex
followed by the body of the packet.
preamble through the MII and asserts RX_DV and CRS simultaneously. (In
10BASE-T loopback, the LXT972M PHY loops back whatever the MAC transmits to it,
including the preamble.)
PHY monitors the connection for link pulses. Once link pulses are detected, data
transmission is enabled and remains enabled as long as either the link pulses or data
transmission continue. If the link pulses stop, the data transmission is disabled.
79.) The slew-rate mechanism allows the
72.
Table 56, Transmit Control
5.8 10 Mbps Operation
Table 50,
Page 42