WJLXT972ALC.A4 Intel, WJLXT972ALC.A4 Datasheet - Page 64

• Manufacturer Part Number: WJLXT972ALC.A4
• Description: IC TRANS 3.3V ETHERNET 64-LQFP
• Manufacturer: Intel
• Type: Transceiverr

Specifications of WJLXT972ALC.A4

• Number Of Drivers/receivers: 1/1
• Protocol: IEEE 802
• Voltage - Supply: 3.14 V ~ 3.45 V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 857341

LXT972M PHY
Datasheet
302875, Revision 5.3
31 October 2007
8.0
Table 39
Cortina Systems
Register Definitions - IEEE Base Registers
This chapter includes definitions for the IEEE base registers used by the LXT972M PHY.
Section 9.0, Register Definitions - Product-Specific Registers
additional product-specific LXT972M PHY registers, which are defined in accordance with
the IEEE 802.3 standard for adding unique device functions.
The LXT972M PHY register set has multiple 16-bit registers.
Register Set for IEEE Base Registers
®
Address
•
•
11 to 14
LXT972M Single-Port 10/100 Mbps PHY Transceiver
Table 39
Table 40
through 8), which are defined in accordance with the “Reconciliation Sublayer and
Media Independent Interface” and “Physical Layer Link Signaling for 10/100 Mbps
Auto-Negotiation” sections of the IEEE 802.3 standard.
10
15
0
1
2
3
4
5
6
7
8
9
Control Register
Status Register #1
PHY Identification Register 1
PHY Identification Register 2
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Base Page Ability Register
Auto-Negotiation Expansion Register
Auto-Negotiation Next Page Transmit Register
Auto-Negotiation Link Partner Next Page Receive Register
1000BASE-T/100BASE-T2 Control Register
1000BASE-T/100BASE-T2 Status Register
Reserved
Extended Status Register
is a register set listing of the IEEE base registers.
through
Table 48
Register Name
provide bit descriptions of the base registers (address 0
8.0 Register Definitions - IEEE
includes definitions of
See
See
See
See
See
See
See
See
See
Not Implemented
Not Implemented
Not Implemented
Not Implemented
Table 40 on page 65
Table 41 on page 66
Table 42 on page 67
Table 43 on page 67
Table 44 on page 68
Table 45 on page 69
Table 46 on page 70
Table 47 on page 70
Table 48 on page 71
Bit Assignments
Base Registers
Page 64