WJLXT972ALC.A4 Intel, WJLXT972ALC.A4 Datasheet - Page 38

no-image

WJLXT972ALC.A4

Manufacturer Part Number
WJLXT972ALC.A4
Description
IC TRANS 3.3V ETHERNET 64-LQFP
Manufacturer
Intel
Type
Transceiverr
Datasheet

Specifications of WJLXT972ALC.A4

Number Of Drivers/receivers
1/1
Protocol
IEEE 802
Voltage - Supply
3.14 V ~ 3.45 V
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
857341

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
WJLXT972ALC.A4
Manufacturer:
INPHI33
Quantity:
5 084
Part Number:
WJLXT972ALC.A4
Manufacturer:
Intel
Quantity:
10 000
Part Number:
WJLXT972ALC.A4
Manufacturer:
INPHI
Quantity:
20 000
Part Number:
WJLXT972ALC.A4
Quantity:
200
Company:
Part Number:
WJLXT972ALC.A4
Quantity:
980
Company:
Part Number:
WJLXT972ALC.A4
Quantity:
940
Part Number:
WJLXT972ALC.A4-857341
Manufacturer:
Cortina
Quantity:
1 643
Part Number:
WJLXT972ALC.A4-857341
Manufacturer:
Cortina Systems Inc
Quantity:
10 000
Part Number:
WJLXT972ALC.A4-857345
Manufacturer:
Cortina
Quantity:
2 456
Part Number:
WJLXT972ALC.A4-857345
Manufacturer:
Cortina Systems Inc
Quantity:
10 000
LXT972M PHY
Datasheet
302875, Revision 5.3
31 October 2007
5.7.3
Figure 17
5.7.3.1
5.7.3.1.1
Cortina Systems
100BASE-X Protocol Sublayer Operations
With respect to the 7-layer communications model, the LXT972M PHY is a Physical Layer
1 (PHY) device.
The LXT972M PHY implements the following sublayers of the reference model defined by
the IEEE 802.3 standard, and discussed from the reference model point of view:
Figure 17
Protocol Sublayers
Physical Coding Sublayer
The Physical Coding Sublayer (PCS) provides the MII interface, as well as the 4B/5B
encoding/decoding function.
For 100BASE-TX operation, the PCS layer provides IDLE symbols to the PMD-layer line
driver as long as TX_EN is de-asserted.
Preamble Handling
When the MAC asserts TX_EN, the PCS substitutes a /J/K symbol pair, also known as the
Start-of-Stream Delimiter (SSD), for the first two nibbles received across the MII. The PCS
layer continues to encode the remaining MII data, following the 4B/5B coding in
until TX_EN is de-asserted. It then returns to supplying IDLE symbols to the line driver.
In the receive direction, the PCS layer performs the opposite function, substituting two
preamble nibbles for the SSD. In 100 Mbps operation, preamble is always passed through
the PCS layer to the MII interface.
®
LXT972M Single-Port 10/100 Mbps PHY Transceiver
Sublayer
Sublayer
Sublayer
Section 5.7.3.1, Physical Coding Sublayer
Section 5.7.3.2, Physical Medium Attachment Sublayer
Section 5.7.3.3, Twisted-Pair Physical Medium Dependent Sublayer
PMA
PMD
PCS
shows the LXT972M PHY protocol sublayers.
LXT97x PHY
Serializer /De-serializer
Link/Carrier Detect
Encoder /Decoder
De-scrambler
Scrambler/
100BASE-TX
MII Interface
5.7 100 Mbps Operation
B3514 -02
Table
Page 38
16,

Related parts for WJLXT972ALC.A4