WJLXT972ALC.A4 Intel, WJLXT972ALC.A4 Datasheet - Page 28

• Manufacturer Part Number: WJLXT972ALC.A4
• Description: IC TRANS 3.3V ETHERNET 64-LQFP
• Manufacturer: Intel
• Type: Transceiverr

Specifications of WJLXT972ALC.A4

• Number Of Drivers/receivers: 1/1
• Protocol: IEEE 802
• Voltage - Supply: 3.14 V ~ 3.45 V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 857341

LXT972M PHY
Datasheet
302875, Revision 5.3
31 October 2007
5.4.4
Table 14
5.5
Note:
Cortina Systems
1. L = Low, and H = High. For LED/CFG pin assignments, see
Auto-Neg.
Disabled
Enabled
Desired Mode
(Mbps)
10/100
Speed
Only
100
100
10
For pin settings used during a hardware reset, see
Settings. During a hardware reset, configuration settings for auto-negotiation and speed
are read in from pins, and register information is unavailable for 1 ms after de-assertion of
the reset.
Hardware Configuration Settings
The LXT972M PHY provides a hardware option to set the initial device configuration. As
listed in
for which provide control bits.
Hardware Configuration Settings
Establishing Link
Figure 6
When a link is established by using parallel detection, the LXT972M PHY sets the duplex
mode to half-duplex, as defined by the IEEE 802.3 standard.
®
• During a software reset, registers are available for reading. To see when the
LXT972M Single-Port 10/100 Mbps PHY Transceiver
during the last hardware reset. Therefore, any changes to pin values made since the
last hardware reset are not detected during a software reset.
LXT972M PHY has completed reset, the reset bit can be polled (that is, register bit
0.15 = 0).
Full or Half
Half Only
Full/Half
Duplex
Table 14,
Half
Half
Half
Full
Full
shows an overview of link establishment for the LXT972M PHY.
1
H
H
H
H
L
L
L
L
Settings
LED/CFG
the hardware option uses the hardware configuration pins, the settings
Pin
H
H
H
H
2
L
L
L
L
H
H
H
H
1
3
L
L
L
L
Auto-
Neg.
0.12
0
1
Control Register
Speed
0.13
Section 3.0, Ball and Pin Assignments
0
0
1
1
1
1
1
1
Duplex
Full-
0.8
Resulting register bit Values
0
1
0
1
0
1
0
1
Section 5.4.4, Hardware Configuration
BASE-TX
Duplex
Full-
100
4.8
Auto-Negotiation Advertisement
0
1
0
1
BASE-
Auto-Negotiation
100
4.7
Advertisement
TX
1
1
1
1
Register
N/A
5.5 Establishing Link
BASE-T
Duplex
Full-
4.6
10
0
0
0
1
BASE-T
Page 28
4.5
10
0
0
1
1