Z16M1720ASG1868 Zilog, Z16M1720ASG1868 Datasheet - Page 172
Z16M1720ASG1868
Manufacturer Part Number
Z16M1720ASG1868
Description
IC PCMCIA INTERFACE 100-VQFP
Manufacturer
Zilog
Datasheet
1.Z0847006PSG.pdf
(330 pages)
Specifications of Z16M1720ASG1868
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
100-LQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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UM008101-0601
< % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
Simultaneous Transfers
The timing for simultaneous transfers and simultaneous transfer/searches is
the same. The DMA is programmed in the Search-Only mode, and both
read and write cycles occur simultaneously in the time that a source-port
read would occur in search-only. Only one address is generated on the
address bus; the I/O port is hardwire-selected during this operation as
shown in the Applications chapter. The IORQ, MREQ, RD, and WR lines
are gated into two new signals by external logic. These signals are either:
MEMWR (Memory write)
IORD (I/O read)
or:
MEMRD (Memory read)
IOWR (I/O write)
Direct Memory Access
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