Z16M1720ASG1868 Zilog, Z16M1720ASG1868 Datasheet - Page 216

• Manufacturer Part Number: Z16M1720ASG1868
• Description: IC PCMCIA INTERFACE 100-VQFP
• Manufacturer: Zilog

Specifications of Z16M1720ASG1868

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 100-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008101-0601
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
Data Bus
D7–D0
*Timing Diagram Refers to Bit Mode Read
IORQ
Port
INT
RD
When reading the PIO, the data returned to the CPU is composed of output
register data from port data lines assigned as outputs and input register data
from port data lines assigned as inputs. The input register contains data that
was present immediately prior to the falling edge of RD. See Figure 10.
An interrupt is generated if interrupts from the port are enabled and the
data on the port data lines satisfies the logical equation defined is not
generated until a change occurs in the status of the logical equation. A
Mode 3 interrupt is generated only when the result of a Mode 3 logical
operation changes from false to true. For example, Mode 3 logical equa-
tion is an OR function. An unmasked port data line becomes active and an
interrupt is requested. If a second unmasked port data line becomes active
concurrently with the first, a new interrupt is not requested because a
change in the result of the Mode 3 logical operation has not occurred.
If the result of a logical operation becomes true immediately prior to or
during M1 an interrupt is requested after the trailing edge of M1
Figure 10.
Φ
Occurs Here
Data Match
Control Mode (Mode 3) Timing
Data Word 1
T
1
T
2
T
W
Data In
Data Word 2
*
T
3
Data Word 1 Placed on Bus
Parallel Input/Output