PI7C9X130DNDE Pericom Semiconductor, PI7C9X130DNDE Datasheet - Page 105

• Manufacturer Part Number: PI7C9X130DNDE
• Description: IC PCIE-PCIX BRIDGE 1PORT 256BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X130DNDE

• Applications: PCI-to-PCI Bridge
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.5.48
7.5.49
PERICOM SEMICONDUCTOR - Confidential
GPIO DATA AND CONTROL REGISTER – OFFSET 78h
SECONDARY INTERRUPT LINE REGISTER – OFFSET 7Ch
Bit
5:4
6
7
8
9
10
11
Bit
15:12
19:16
23:20
27:24
31:28
Function
VGA Enable
VGA 16-bit Decode
Master Abort Mode
Primary Master
Timeout
Secondary Master
Timeout
Master Timeout
Status
Discard Timer
SERR_L Enable
Function
GPIO Output Write-
1-to-Clear
GPIO Output Write-
1-to-Set
GPIO Output Enable
Write-1-to-Clear
GPIO Output Enable
Write-1-to-Set
GPIO Input Data
Register
Type
Type
RWC
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
Page 105 of 165
Description
00: VGA memory and I/O transactions on the primary and secondary interfaces
are ignored, unless decoded by other mechanism
01: VGA memory and I/O transactions on the primary interface are forwarded
to secondary interface without address translation, but VGA transactions on
secondary interface are ignored
10: VGA memory and I/O transactions on the secondary interface are
forwarded to primary interface without address translation, but VGA
transactions on primary interface are ignored
Reset to 00
0: Execute 10-bit address decodes on VGA I/O accesses
1: Execute 16-bit address decode on VGA I/O accesses
Reset to 0
0: Do not report master aborts (return FFFFFFFFh on reads and discards data
on write)
1: Report master abort by signaling target abort if possible or by the assertion
of SERR_L (if enabled).
Reset to 0
0: Primary discard timer counts 2
1: Primary discard timer counts 2
FORWARD BRIDGE –
Bit is RO and ignored by PI7C9X130
Reset to 0
0: Secondary discard timer counts 2
1: Secondary discard timer counts 2
REVERSE BRIDGE –
Bit is RO and ignored by PI7C9X130
Reset to 0
Bit is set when the discard timer expires and a delayed completion is discarded
at the PCI interface for the forward or reverse bridge
Reset to 0
Bit is set to enable to generate ERR_NONFATAL or ERR_FATAL for forward
bridge, or assert SERR_L for reverse bridge as a result of the expiration of the
discard timer. It has no meaning if PI7C9X130 is in PCI-X mode.
Reset to 0
Description
Reset to 0h
Reset to 0h
Reset to 0h
Reset to 0h
Reset to 0h
PCI EXPRESS TO PCI-X BRIDGE
15
10
PCI clock cycles
PCI clock cycles
15
10
PCI clock cycles
PCI clock cycles
Mar 2010 - Rev 2.0
PI7C9X130