PI7C9X130DNDE Pericom Semiconductor, PI7C9X130DNDE Datasheet - Page 83

• Manufacturer Part Number: PI7C9X130DNDE
• Description: IC PCIE-PCIX BRIDGE 1PORT 256BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X130DNDE

• Applications: PCI-to-PCI Bridge
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.5 PCI CONFIGURATION REGISTERS FOR NON-TRANSPARENT
7.5.1 VENDOR ID – OFFSET 00h
7.5.1
7.5.2
PERICOM SEMICONDUCTOR - Confidential
BRIDGE MODE
DEVICE ID – OFFSET 00h
PRIMARY COMMAND REGISTER – OFFSET 04h
The following section describes the configuration space when the device is in non-transparent bridge
mode. The descriptions for different register type are listed as follow:
Register Type
RO
ROS
RW
RO(WS)
RWC
RWS
RWCS
Bit
15:0
Bit
31:16
Bit
0
1
2
3
4
Function
Vendor ID
Function
Device ID
Function
I/O Space Enable
Memory Space
Enable
Bus Master Enable
Special Cycle
Enable
Memory Write and
Invalidate Enable
Type
Type
Type
RW
RW
RW
RO
RO
RO
RO
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Descriptions
Read Only
Read Only and Sticky
Read/Write
Read Only at primary interface and Read/Write at secondary interface
Read/Write “1” to clear
Read/Write and Sticky
Read/Write “1” to clear and Sticky
Description
Identifies Pericom as the vendor of this device. Returns 12D8h when read.
Description
Identifies this device as the PI7C9X130. Returns E130 when read.
Description
0: Ignore I/O transactions on the primary interface
1: Enable response to memory transactions on the primary interface
Reset to 0
0: Ignore memory read transactions on the primary interface
1: Enable memory read transactions on the primary interface
Reset to 0
0: Do not initiate memory or I/O transactions on the primary interface and
disable response to memory and I/O transactions on the secondary interface
1: Enable the PI7C9X130 to operate as a master on the primary interfaces for
memory and I/O transactions forwarded from the secondary interface. If the
primary of the reverse bridge is PCI-X mode, the PI7C9X130 is allowed to
initiate a split completion transaction regardless of the status bit.
Reset to 0
0: Bridge does not respond as a target to Special Cycle transactions, so this
bit is defined as Read-Only and must return 0 when read
Reset to 0
0: PI7C9X130 does not originate a Memory Write and Invalidate transaction.
Implements this bit as Read-Only and returns 0 when read (unless forwarding a
transaction for another master). This bit will be ignored in PCI-X mode.
Reset to 0
PCI EXPRESS TO PCI-X BRIDGE
Mar 2010 - Rev 2.0
PI7C9X130