PI7C9X130DNDE Pericom Semiconductor, PI7C9X130DNDE Datasheet - Page 89

• Manufacturer Part Number: PI7C9X130DNDE
• Description: IC PCIE-PCIX BRIDGE 1PORT 256BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X130DNDE

• Applications: PCI-to-PCI Bridge
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.5.14
7.5.15
7.5.16
7.5.17
7.5.18
PERICOM SEMICONDUCTOR - Confidential
DOWNSTREAM MEMORY 3 UPPER BASE ADDRESS REGISTER – OFFSET 24h
RESERVED REGISTER – OFFSET 28h
SUBSYSTEM ID AND SUBSYSTEM VENDOR ID REGISTER – OFFSET 2Ch
RESERVED REGISTER – OFFSET 30h
CAPABILITY POINTER – OFFSET 34h
Bit
31:12
Bit
31:0
Bit
15:0
31:16
Bit
7:0
31:8
Function
Base Address
Function
Base address
Function
Subsystem Vendor
ID
Subsystem ID
Function
Capability Pointer
Reserved
Type
Type
Type
Type
RW/RO
RO/RW
RO
RO
RO
RO
Page 89 of 165
Description
The size and type of this Base Address Register are defined from Downstream
Memory 3 Setup Register (CSR Offset 014h), which can be initialized by
EEPROM (I2C) or SM Bus or Local Processor. Writing a zero to bit [31] of
the setup registers (CSR Offset 014h and 018h) to disable this register. The
range of this register is from 4KB to 9EB for memory space.
uses Memory 3 Translated Base Register (CSR Offset 010h) to formulate direct
address translation when 32-bit addressing programmed. When 64-bit
addressing programmed, no address translation is performed. If a bit in the
setup register is set to one, then the correspondent bit of this register will be
changed to RW.
Reset to 00000h
Description
The size of this Base Address Register is defined from Downstream Memory 3
Upper 32-bit Setup Register (CSR Offset 018h), which can be initialized by
EEPROM (I2C) or SM Bus or Local Processor. Writing a zero to bit [31] of
the setup registers (CSR Offset 018h) to disable this register. This register
defines the upper 32 bits of a memory range for downstream forwarding
memory. If a bit in the setup register is set to one, then the correspondent bit
of this register will be changed to RW.
Reset to 00000000h
Description
Identify the vendor ID for add-in card or subsystem
Reset to 0000h
Identify the vendor specific device ID for add-in card or subsystem
Reset to 0000h
Description
Capability pointer to 80h
Reset to 80h
Reset to 0
PCI EXPRESS TO PCI-X BRIDGE
Mar 2010 - Rev 2.0
PI7C9X130
PI7C9X130