PI7C9X130DNDE Pericom Semiconductor, PI7C9X130DNDE Datasheet - Page 134

• Manufacturer Part Number: PI7C9X130DNDE
• Description: IC PCIE-PCIX BRIDGE 1PORT 256BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X130DNDE

• Applications: PCI-to-PCI Bridge
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.6 CONTROL AND STATUS REGISTERS FOR NON-TRANSPARENT
7.6.1
7.6.2
7.6.3
PERICOM SEMICONDUCTOR - Confidential
BRIDGE MODE
RESERVED REGISTERS – OFFSET 000h TO 004h
DOWNSTREAM MEMORY 2 TRANSLATED BASE REGISTER – OFFSET 008h
DOWNSTREAM MEMORY 2 SETUP REGISTER – OFFSET 00Ch
Control and Status Registers (CSRs) can be accessed by Memory or I/O transactions from both primary
and secondary ports. The CSRs are defined and to be used along with configuration registers (see
previous section 7.5 for details) for non-transparent bridge operations.
Register Type
RO
ROS
RW
RO(WS)
RWC
RWS
RWCS
Bit
11:0
31:12
Bit
0
2:1
3
11:4
30:12
31
Function
Reserved
Downstream
Memory 2
Translated Base
Function
Type Selector
Address Type
Prefetchable Control
Reserved
Base Address
Register Size
Base Address
Register Enable
RO (WS)
RO (WS)
RO (WS)
Type
Type
(WS)
RW
RO
RO
RO
RO
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Descriptions
Read Only
Read Only and Sticky
Read/Write
Read Only at primary interface and Read/Write at secondary interface
Read/Write “1” to clear
Read/Write and Sticky
Read/Write “1” to clear and Sticky
Description
Reset to 000h
Define the translated base address for downstream memory transactions whose
initiator addresses fall into Downstream Memory 2 address range. The number
of bits that are used for translated base is determined by its setup register (offset
00Ch)
Reset to 00000h
Description
0: Memory space is requested
Reset to 0
00: 32-bit address space
01: 64-bit address space
Reset to 00
0: Non-prefetchable
1: Prefetchable
Reset to 0
Reset to 00
0: Set the corresponding bit in the Base Address Register to read only
1: Set the corresponding bit in the Base Address Register to read/write in order
to control the size of the address range
Reset to 00000h
0: Disable this Base Address Register
1: Enable this Base Address Register
Reset to 0
PCI EXPRESS TO PCI-X BRIDGE
Mar 2010 - Rev 2.0
PI7C9X130