PI7C9X130DNDE Pericom Semiconductor, PI7C9X130DNDE Datasheet - Page 88

• Manufacturer Part Number: PI7C9X130DNDE
• Description: IC PCIE-PCIX BRIDGE 1PORT 256BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X130DNDE

• Applications: PCI-to-PCI Bridge
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.5.12
7.5.13
PERICOM SEMICONDUCTOR - Confidential
DOWNSTREAM MEMORY 2 BASE ADDRESS REGISTER – OFFSET 1Ch
DOWNSTREAM MEMORY 3 BASE ADDRESS REGISTER – OFFSET 20h
Bit
3
11:4
31:12
Bit
0
2:1
3
11:4
31:12
Bit
0
2:1
3
11:4
Function
Prefetchable control
Reserved
Base Address
Function
Space Indicator
Address Type
Prefetchable control
Reserved
Base Address
Function
Space Indicator
Address Type
Prefetchable control
Reserved
Type
Type
Type
RW/RO
RW/RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Page 88 of 165
Description
0: Memory space is non-prefetchable
1: Memory space is prefetchable
Reset to 0
Reset to 0
The size and type of this Base Address Register are defined from Downstream
IO or Memory 1 Setup Register (Offset ACh), which can be initialized by
EEPROM (I2C) or SM Bus or Local Processor. Writing a zero to bit [31] of
the setup register to disable this register. The range of this register is from 4KB
to 2GB for memory space or from 64B to 256B for IO space.
uses downstream IO or Memory 1 Translated Base Register (Offset A8h) to
formulate direct address translation. If a bit in the setup register is set to one,
then the correspondent bit of this register will be changed to RW.
Reset to 00000h
Description
0: Memory space
1: IO space
Reset to 0
00: 32-bit address decode range
01, 10 and 11: reserved
Reset to 00
0: Memory space is non-prefetchable
1: Memory space is prefetchable
Reset to 0
Reset to 0
The size and type of this Base Address Register are defined from Downstream
Memory 2 Setup Register (CSR Offset 00Ch), which can be initialized by
EEPROM (I2C) or SM Bus or Local Processor. Writing a zero to bit [31] of
the setup register to disable this register. The range of this register is from 4KB
to 2GB for memory space.
Translated Base Register (CSR Offset 008h) to formulate direct address
translation. If a bit in the setup register is set to one, then the correspondent
bit of this register will be changed to RW.
Reset to 00000h
Description
0: Memory space
1: IO space
Reset to 0
00: 32-bit address decode range
01: 64-bit address decode range
10 and 11: reserved
Reset to 00
0: Memory space is non-prefetchable
1: Memory space is prefetchable
Reset to 0
Reset to 0
PI7X9X110A uses downstream Memory 2
PCI EXPRESS TO PCI-X BRIDGE
Mar 2010 - Rev 2.0
PI7X9X110A
PI7C9X130