PI7C9X130DNDE Pericom Semiconductor, PI7C9X130DNDE Datasheet - Page 108

• Manufacturer Part Number: PI7C9X130DNDE
• Description: IC PCIE-PCIX BRIDGE 1PORT 256BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X130DNDE

• Applications: PCI-to-PCI Bridge
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PERICOM SEMICONDUCTOR - Confidential
Bit
7:3
15:8
16
17
18
19
20
21
31:22
Function
Device Number
Bus Number
64-bit Device on
Primary Bus
Interface
133MHz Capable
Split Completion
Discarded
Unexpected Split
Completion
Split Completion
Overrun
Split Request
Delayed
Reserved
Type
RWC
RWC
RWC
RWC
RO /
RO
RO
RO
RO
RO
Page 108 of 165
Description
Device number (AD [15:11] of a type 0 configuration transaction) is assigned
to the PI7C9X130 by the connection of system hardware. Each time the
PI7C9X130 is addressed by a configuration write transaction, the bridge
updates this register with the contents of AD [15:11] of the address phase of the
configuration transaction, regardless of which register in the PI7C9X130 is
addressed by the transaction. The PI7C9X130 is addressed by a configuration
write transaction if all of the following are true:




Reset to 11111
Additional address from which the contents of the primary bus number register
on type 1 configuration space header is read. The PI7C9X130 uses the bus
number, device number, and function number fields to create a completer ID
when responding with a split completion to a read of an internal PI7C9X130
register. These fields are also used for cases when one interface is in
conventional PCI mode and the other is in PCI-X mode.
Reset to 11111111
64-bit supported when DEV64 is set to high
Reset to 0 in forward bridge mode or in reverse bridge mode with REQ64_L is
high at the de-assertion of RESET_L or reset to 1 in reverse bridge mode with
REQ64_L is low at the de-assertion of RESET_L
When this bit is 1, PI7C9X130 is 133MHz capable on its primary bus interface
Reset to 0 in forward bridge mode or 1 in reverse bridge mode
This bit is a read-only and set to 0 in reverse bridge mode or is read-write in
forward bridge mode
When this is set to 1, a split completion has been discarded by PI7C9X130 at
primary bus because the requester did not accept the split completion
transaction
Reset to 0
This bit is set to 0 in forward bridge mode or is read-write in reverse bridge
mode
When this is set to 1, an unexpected split completion has been received with the
requester ID equaled to the primary bus number, device number, and function
number at the PI7X9X130 primary bus interface
Reset to 0
When this bit is set to 1, a split completion has been terminated by PI7C9X130
with either a retry or disconnect at the next ADB due to the buffer full
condition
Reset to 0
When this bit is set to 1, a split request is delayed because PI7C9X130 is not
able to forward the split request transaction to its primary bus due to
insufficient room within the limit specified in the split transaction commitment
limit field of the downstream split transaction control register
Reset to 0
0000000000
The transaction uses a configuration write command
IDSEL is asserted during the address phase
AD [1:0] are 00 (type o configuration transaction)
AD [10:8] of the configuration address contain the appropriate function
number
PCI EXPRESS TO PCI-X BRIDGE
Mar 2010 - Rev 2.0
PI7C9X130