PI7C9X130DNDE Pericom Semiconductor, PI7C9X130DNDE Datasheet - Page 36

• Manufacturer Part Number: PI7C9X130DNDE
• Description: IC PCIE-PCIX BRIDGE 1PORT 256BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X130DNDE

• Applications: PCI-to-PCI Bridge
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.2 PCI EXPRESS EXTENDED CAPABILITY REGISTER MAP
PERICOM SEMICONDUCTOR - Confidential
Note
Note
Note
Note
Note
PI7C9X130 also supports PCI Express Extended Capabilities with from 257-byte to 4096-byte space.
The offset range is from 100h to FFFh. The offset 100h is defined for Advance Error Reporting
(ID=0001h). The offset 150h is defined for Virtual Channel (ID=0002h).
Figure 7-11 PCI Express Extended Capability Register Map (100h – FFFh)
Primary Bus
Configuration
Access for both
Transparent and
Non-transparent
mode or
Secondary Bus
Configuration
Access for
Transparent
Mode
103h – 100h
107h – 104h
10Bh – 108h
10Fh – 10Ch
113h – 110h
117h – 114h
11Bh – 118h
12Bh – 11Ch
12Fh – 12Ch
133h – 130h
137h – 134h
13Bh – 138h
14Bh – 13Ch
14Fh – 14Ch
153h – 150h
157h – 154h
1
2
3
4
5
: When masquerade is enabled, it is pre-loadable.
: When both masquerade and non-transparent mode are enabled, it is pre-loadable.
: When non-transparent mode is enabled, it is pre-loadable.
: The VPD data is read/write through I2C during VPD operation.
: Read access only.
Secondary
Bus
Configuration
Access for
Non-
Transparent
Mode only
103h – 100h
107h – 104h
10Bh – 108h
10Fh – 10Ch
113h – 110h
117h – 114h
11Bh – 118h
12Bh – 11Ch
12Fh – 12Ch
133h – 130h
137h – 134h
13Bh – 138h
14Bh – 13Ch
14Fh – 14Ch
153h – 150h
157h – 154h
Page 36 of 165
Transparent
Mode (type1)
Advanced Error
Reporting
(AER)
Capability
Uncorrectable
Error Status
Uncorrectable
Error Mask
Uncorrectable
Severity
Correctable
Error Status
Correctable
Error Mask
AER Control
Header Log
Register
Secondary
Uncorrectable
Error Status
Secondary
Uncorrectable
Error Mask
Secondary
Uncorrectable
Severity
Secondary AER
Control
Secondary
Header Log
Register
Reserved
VC Capability
Port VC
Capability 1
Non-
Transparent
Mode
(Type0)
Advanced Error
Reporting
(AER)
Capability
Uncorrectable
Error Status
Uncorrectable
Error Mask
Uncorrectable
Severity
Correctable
Error Status
Correctable
Error Mask
AER Control
Header Log
Register
Secondary
Uncorrectable
Error Status
Secondary
Uncorrectable
Error Mask
Secondary
Uncorrectable
Severity
Secondary AER
Control
Secondary
Header Log
Register
Reserved
VC Capability
Port VC
Capability 1
PCI EXPRESS TO PCI-X BRIDGE
(I2C) Access
EEPROM
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Mar 2010 - Rev 2.0
SM Bus
Access
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
PI7C9X130
5