PI7C9X130DNDE Pericom Semiconductor, PI7C9X130DNDE Datasheet - Page 148

• Manufacturer Part Number: PI7C9X130DNDE
• Description: IC PCIE-PCIX BRIDGE 1PORT 256BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X130DNDE

• Applications: PCI-to-PCI Bridge
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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PERICOM SEMICONDUCTOR - Confidential
RESET SCHEME
PI7C9X130 also supports subsystem vendor and subsystem ID. PI7C9X130 will ignore target response
while the bus is idle.
PRSNT1# and PRSNT2# are not implemented on both PI7C9X130. The use of these two signals is
mandatory on an add-in card in order to support hot-plug.
PI7C9X130 requires the fundamental reset (PERST_L) input for internal logic when it is set as forward
bridge mode. PI7C9X130 requires the PCI/PCI-X reset (RESET_L) input when it is set as reverse
bridge mode. Also, PI7C9X130 has a power-on-reset (POR) circuit to detect VDDCAUX power supply
for auxiliary logic control.
Cold Reset:
A cold reset is a fundamental or power-on reset that occurs right after the power is applied to PI7C9X130
(during initial power up). See section 7.1.1 of PCI Express to PCI/PCI-X Bridge Specification,
Revision 1.0 for details.
Warm Reset:
A warm reset is a reset that triggered by the hardware without removing and re-applying the power
sources to PI7C9X130.
Hot Reset:
A hot reset is a reset that used an in-band mechanism for propagating reset across a PCIe link to
PI7C9X130. PI7C9X130 will enter to training control reset when it receives two consecutive TS1 or
TS2 order-sets with reset bit set.
DL_DOWN Reset:
If the PCIe link goes down, the Transaction and Data Link Layer will enter DL_DOWN status.
PI7C9X130 discards all transactions and returns all logic and registers to initial state except the sticky
registers.
Upon receiving reset (cold, warm, hot, or DL_DOWN) on PCIe interface, PI7C9X130 will generate
PCI/PCI-X reset (RESET_L) to the downstream devices on the PCI/PCI-X bus in forward bridge mode.
The PCI/PCI-X reset de-assertion follows the de-assertion of the reset received from PCIe interface.
The reset bit of Bridge Control Register may be set depending on the application. PI7C9X130 will
tolerant to receive and process SKIP order-sets at an average interval between 1180 to 1538 Symbol
Times. PI7C9X130 does not keep PCI/PCI-X reset active when VD33 power is off even though VAUX
(3.3v) is supported. It is recommended to add a weak pull-down resistor on its application board to
ensure PCI/PCI-X reset is low when VD33 power is off (see section 7.3.2 of PCI Bus Power
management Specification Revision 1.1).
In reverse bridge mode, PI7C9X130 generates fundamental reset (PERST_L) and then 1024 TS1 order-
sets with reset bit set when PCI/PCI-X reset (RESET_L) is asserted to PI7C9X130. PI7C9X130 has
scheduling skip order-set for insertion at an interval between 1180 and 1538 Symbol Times.
PI7C9X130 transmits one Electrical Idle order-set and enters to Electrical Idle.
Page 148 of 165
PCI EXPRESS TO PCI-X BRIDGE
Mar 2010 - Rev 2.0
PI7C9X130