MRF89XAT-I/MQ Microchip Technology, MRF89XAT-I/MQ Datasheet
MRF89XAT-I/MQ
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MRF89XAT-I/MQ Summary of contents
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... Ultra-Low Power, Integrated ISM Band © 2010 Microchip Technology Inc. MRF89XA Data Sheet Sub-GHz Transceiver Preliminary DS70622B ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Integrated Power Amplifier (PA) and Low Noise Amplifiers (LNA) • Channel filters • On-chip IF gain and mixers • Integrated low-phase noise VCO © 2010 Microchip Technology Inc. Sub-GHz Transceiver Baseband Features • Packet handling feature with data whitening and automatic CRC generation • ...
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... Note 1: Pin 33 (GND) is located on the underside of the IC package recommended to connect Pin 32 (NC) to GND. DS70622B-page 4 Pin Diagram Figure 1 illustrates the top view pin arrangement of the The RF 32-pin QFN package (1) 33 GND MRF89XA Preliminary 25 TEST2 24 PLOCK 23 IRQ1 22 IRQ0 21 DATA 20 CLKOUT 19 SCK 18 SDI 17 16 © 2010 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2010 Microchip Technology Inc. Preliminary MRF89XA DS70622B-page 5 ...
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... MRF89XA NOTES: DS70622B-page 6 Preliminary © 2010 Microchip Technology Inc. ...
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... OVERVIEW Microchip Technology's MRF89XA is a fully integrated, half-duplex, sub-GHz transceiver. This low-power, single chip FSK and OOK baseband transceiver supports: • Superheterodyne architecture • Multi-channel, multi-band synthesizer with Phase Lock Loop (PLL) for easy RF design • Power Amplifier (PA) • Low Noise Amplifier (LNA) • ...
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FIGURE 1-1: MRF89XA SIMPLIFIED BLOCK DIAGRAM Reception Block First Stage LNA Mixers LO1 RX RFIO X LO1 TX I Second PA Stage Q Mixers Transmission Block For General Biasing Supply Block DVRS x Supply RSSI I Second Filtering/ Stage IF ...
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FIGURE 1-2: MRF89XA TO MICROCONTROLLER INTERFACE (NODE) BLOCK DIAGRAM Antenna Matching Saw Circuitry Filter Block The interface between the MRF89XA and the MCU depends on the Data mode of operation. For more information refer to Section 3.8 “Data Note: Processing”. ...
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... MRF89XA NOTES: DS70622B-page 10 Preliminary © 2010 Microchip Technology Inc. ...
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... The device operates in the low-voltage range of 2.1V to 3.6V, and in Sleep mode, it operates at a very low-current state, typically 0.1 µA. © 2010 Microchip Technology Inc. The frequency synthesizer is based on an integer-N PLL having PLL bandwidth of 15k Hz. Two programmable frequency dividers in the feedback loop ...
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... OSC2 DS70622B-page 12 I LO2 LO1 LO2 TX Q RSSI OOK Demod FSK LO2 RX Demod LO1 RX I LO2 Generator I LO1 LO2 TX Q Preliminary Waveform Generator IRQ0 IRQ1 BitSync SDI Control SDO SCK CSCON CSDAT CLKOUT DATA TEST<8:0> PLOCK © 2010 Microchip Technology Inc. ...
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... RFIO Analog I — 33 Vss Ground © 2010 Microchip Technology Inc. Description Test Pin. Connected to Ground during normal operation. Test Pin. Connected to Ground during normal operation. VCO tank. VCO tank. PLL loop filter. PLL loop filter. Test Pin. Connected to Ground during normal operation. ...
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... AVRS INTS V DVRS INTS V VCORS INTS V PARS DD Preliminary pin have two bypass DD pin DD PA Regulator 1.80 V Biasing Driver - Ext. PA Choke VCORS PARS Pin 29 Pin 3 0.047 µF X7R Regulated Voltage (in Volts) 2.1-3.6 DD 1.4 DD 1.0 1.0 0.85 1.8 © 2010 Microchip Technology Inc. ...
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... PA Regulator (1.8V RFIO Antenna LNA © 2010 Microchip Technology Inc. The PA and the LNA front-ends in the MRF89XA, which share the same Input/Output pin, are internally matched to approximately 50Ω. 2.4 Filters and Amplifiers Block 2.4.1 INTERPOLATION FILTER After digital-to-analog conversion during transmission, both I and Q signals are smoothed by interpolation filters ...
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... The guidelines for selecting the appropriate crystal with specifications are explained in Section 4.6 “Crystal Specification and Selection Guidelines”. Crystal frequency error will directly trans- Note: late to carrier frequency (F frequency deviation error. Preliminary LO PLLN VCOTP VCOTN VCORS ), bit rate and rf © 2010 Microchip Technology Inc. ...
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... FIGURE 2-5: LO VCO OUTPUT GENERATOR LO VCO Output © 2010 Microchip Technology Inc. 2.5.3.1 The MRF89XA features a PLL lock detect indicator (PLOCK). This is useful for optimizing power consump- tion, by adjusting the synthesizer wake-up time. The lock status can also be read on the LSTSPLL bit from the FTPRIREG register (Register 2-15), and must be cleared by writing a ‘ ...
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... CSCON has priority over CSDAT. Input Input Input Input Input Input Output only if CSCON or CSDAT = 0. Input Input Input Input Input Input (1) Output Output (1) Output Output Input Output Input Output Output Output (2) (2) (2) Output Output Preliminary Comment © 2010 Microchip Technology Inc. ...
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... FIGURE 2-6: TRANSMITTER ARCHITECTURE BLOCK DIAGRAM up-conversion Amplification RFIO PA RF © 2010 Microchip Technology Inc. 2.9 Transmitter The transmitter chain is based on the same double-conversion architecture and uses the same intermediate frequencies as the receiver chain. The main blocks include: A digital waveform generator that provides the I and Q ...
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... Similarly, in Receive mode, the shift register gets bit-by-bit data from the demodulator and writes them byte-by-byte to the FIFO.These details are illustrated in Figure 2-7. dev 1 Fdev I(t) Q(t) Preliminary © 2010 Microchip Technology Inc. ...
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... First down-conversion down-conversion LNA LO1 RX IF1 RF © 2010 Microchip Technology Inc. 2.10.1 RECEIVER ARCHITECTURE Figure 2-8 illustrates the receiver architecture block diagram. The first IF is one-ninth of the RF frequency (approximately down-conversion down-converts the I and Q signals to baseband in the case of the FSK receiver (zero-IF) and to a low-IF (IF2) for the OOK receiver ...
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... FIFO. (FIFO Interrupts can be used to manage the FIFO content). CSCON SDI SPI CONFIG SDO (Slave) SCK SPI DATA (Slave) CSDAT Preliminary Frequency LO1 RX Channel Image Channel Frequency LO1 RX Frequency I/O SDI SDO SCK I/O ® PIC Microcontroller (Master) © 2010 Microchip Technology Inc. ...
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... Microchip Technology Inc. The MRF89XA supports SPI mode 0,0, which requires the SCK to remain idle in a low state. The CS pins, ...
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... A1, the current content of A1 can be read by the µC. DS70622B-page A(2) A(1) A(0) stop D(7) D(6) D( D(7) D(6) D(5) (In)/(Out) refers to MRF89XA side Preliminary New value at address A1 D(4) D(3) D(2) D(1) D(0) Current value at address A1* D(4) D(3) D(2) D(1) D(0) HZ (input) © 2010 Microchip Technology Inc. ...
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... CSCON back high between two read sequences. The bytes are alternatively considered as address and value. FIGURE 2-13: READ REGISTER SEQUENCE CSCON (In) SCK (In) SDI (In) start rw A(4) A(3) Address = A1 x SDO (Out (input) © 2010 Microchip Technology Inc A(2) A(1) A(0) stop D(7) D(6) D(5) Preliminary MRF89XA 12 13 ...
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... WRITE BYTES SEQUENCE (EXAMPLE DIAGRAM FOR 2 BYTES CSDAT (In) SCK (In byte written SDI (In) D1(7) D1(6) D1(5) D1(4) D1(3) D1(2) D1(1) x SDO (Out (input) DS70622B-page D1(0) D2(7) D2(6) D2(5) D2(4) D2(3) D2(2) D2(1) D2( (input) Preliminary byte written (input) © 2010 Microchip Technology Inc. ...
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... FIGURE 2-15: READ BYTES SEQUENCE (EXAMPLE DIAGRAM FOR 2 BYTES CSDAT (In) SCK (In) SDI (In First byte read D1(7) D1(6) D1(5) D1(4) D1(3) D1(2) D1(1) SDO (Out) HZ (input) © 2010 Microchip Technology Inc D1(0) D2(7) D2(6) D2(5) D2(4) D2(3) D2(2) D2(1) D2(0) HZ (input) Preliminary ...
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... The memory in the MRF89XA transceiver is implemented as static RAM and is accessible through the SPI port. The memory configuration of the MRF89XA is illustrated in Figure 2-17 and Figure 2-18. FIFO LSB 0x00 Transmit/Receive FIFO 0x40 SHIFT REGISTER (8 bits) 1 MSB Preliminary 64 bytes © 2010 Microchip Technology Inc. ...
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... The FIFO serves as a buffer for data transmission and reception. There is a shifted register (SR) to handle bit shifts for the FIFO during transmission and reception. POR sets default values in all Configuration/Control /Status registers. © 2010 Microchip Technology Inc. Register Name FILCREG 0x10 PFCREG ...
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... Selects the central frequency of the polyphase filter Enables polyphase filter (in OOK receive mode, bit synchronizer control, Sync word recognition, Sync word size, Sync word error Reserved for future use Preliminary Related Control Functions Related Control Functions Related Control Functions © 2010 Microchip Technology Inc. ...
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... Node Address Set Register 0x1E PKTCREG Packet Configuration Register 0x1F FCRCREG FIFO CRC Configuration Register © 2010 Microchip Technology Inc. Register Description RSSI output RSSI threshold size in OOK demodulator, RSSI threshold period in OOK demodulator, cut-off frequency of the OOK threshold in demodulator Register Description ...
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... This bit selects between the two sets of frequency dividers of the PLL, Ri/Pi/Si. For more information, see Section 3.2.7 “Frequency Calculation” Enable R2/P2/S2 set 0 = Enable R1/P1/S1 set (default) DS70622B-page 32 R/W-0 R/W-1 R/W-0 FBS<1:0> VCOT<1:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 RPS bit Bit is unknown © 2010 Microchip Technology Inc. ...
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... TABLE 2-7: DATA OPERATION MODE SETTINGS Data Operation DMODE1 Mode Continuous 0 (default mode) Buffer 0 Packet 0/1) © 2010 Microchip Technology Inc. R/W-0 R/W-1 OOKTYP<1:0> DMODE1 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) DMODE0 0 1 Preliminary MRF89XA R/W-0 ...
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... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared = 100 kHz (default) dev R/W-0 R/W-0 BRVAL<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared /64 * (BRVAL + 1) ] xtal Preliminary R/W-0 R/W-1 R/W-1 bit Bit is unknown R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2010 Microchip Technology Inc. ...
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... Setting these bits selects the FIFO threshold for interrupt source. Refer to Section 3.6.2 “Interrupt Sources and Flags” for additional information. FTINT<5:0> = 001111 (default) FIFO_THRESHOLD interrupt source’s behavior depends on the running mode (TX Stand-by mode). © 2010 Microchip Technology Inc. R/W-0 R/W-1 R/W-1 FTOVAL<7:0> ...
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... R/W-0 R/W-1 R1CVAL<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-1 P1CVAL<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 bit Bit is unknown R/W-0 R/W-0 bit Bit is unknown © 2010 Microchip Technology Inc. ...
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... R2CVAL<7:0>: R2 Value bits These bits indicate the value in R2 counter to generate carrier frequencies in FSK mode. R2CVAL<7:0> = 0x74 (default) R2CVAL is activated if RPS = 1 in GCONREG. Also default values R2, P2 and S2 generate 920 MHz in FSK Mode. © 2010 Microchip Technology Inc. R/W-1 R/W-0 R/W-0 S1CVAL<7:0> ...
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... R/W-0 R/W-0 P2CVAL<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-0 R/W-0 S2CVAL<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-0 bit Bit is unknown R/W-1 R/W-1 bit Bit is unknown © 2010 Microchip Technology Inc. ...
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... These bits control the RAMP rise and fall times of the TX PA regulator output voltage in OOK mode µs (default µ 8.5 µ µs bit 2-0 Reserved: Reserved bits; do not use 000 = Reserved (default) © 2010 Microchip Technology Inc. R/W-1 R/W-1 r PARC<1:0> — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... FIFOFULL U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Continuous Mode (default) Buffer Mode Packet Mode (3) (if address filtering is enabled) Continuous Mode (default) Buffer Mode (1) Packet Mode (1) Preliminary R/W-0 R/W-0 FIFOEMPTY FOVRRUN bit Bit is unknown © 2010 Microchip Technology Inc. ...
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... No FIFO Overrun occurred Writing a ‘1’ for this bit clears flag and FIFO. Note 1: This mode is also available in Stand-by mode. 2: PLREADY = Payload ready 3: ADRSMATCH = Address Match © 2010 Microchip Technology Inc. Continuous Mode (default): Buffer Mode or 1x Packet Mode: Preliminary MRF89XA ...
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... IRQ0/IRQ1 or not. DS70622B-page 42 R/W-0 r R/W-0 IRQ0TXST — RIRQS U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared sync word has been detected) Buffer Mode: Packet Mode: (1) Preliminary R/W-0 R/W-1 LSTSPLL LENPLL bit Bit is unknown © 2010 Microchip Technology Inc. ...
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... The PLL lock detect flag is mapped to the PLOCK pin (pin 23), and pin High-Z pin Note 1: Setting this bit to ‘0’ disables the RSSI IRQ source. It can be left enabled at any time, and the user can choose to map this interrupt to IRQ0/IRQ1 or not. © 2010 Microchip Technology Inc. Preliminary MRF89XA ...
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... RTIVAL<7:0>: RSSI Threshold for Interrupt Value bits These bits indicate the RSSI threshold value for interrupt request RTIVAL<7:0> = 00000000 (default) DS70622B-page 44 R/W-0 R/W-0 R/W-0 RTIVAL<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit Bit is unknown © 2010 Microchip Technology Inc. ...
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... Note © 2010 Microchip Technology Inc. R/W-0 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared – 100 kHz (default MHz/12.8 MHz BUTFILV)/8 = 12.8 MHz. xtal ...
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... Reserved<3:0>: Reserved bits; do not use 1000 = Reserved (default) DS70622B-page 46 R/W-1 r — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared = 100 kHz (default Preliminary — — bit Bit is unknown © 2010 Microchip Technology Inc. ...
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... These bits indicate the number of errors tolerated in the SYNC word recognition Errors Errors Errors Errors (default) bit 0 Reserved: Reserved bit; do not use 0 = Reserved (default) © 2010 Microchip Technology Inc. R/W-1 R/W-1 R/W-0 SYNCWSZ<1:0> SYNCTEN<1:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (ADDRESS:0x14) R-0 R-1 R-0 RSSIVAL<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2010 Microchip Technology Inc — — bit Bit is unknown R-0 R-0 bit Bit is unknown ...
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... These bits set the cut-off frequency of the averaging for the average mode of the OOK threshold in the demodulator. ( BR/32.π Reserved; do not use 01 = Reserved; do not use BR/8.π (default) c © 2010 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 OOKTHPV<2:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary MRF89XA R/W-0 R/W-0 OOKATHC< ...
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... R/W-0 R/W-0 SYNCV<31:24> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 SYNCV<23:16> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit Bit is unknown © 2010 Microchip Technology Inc. ...
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... Bit is set r = Reserved bit 7-0 SYNCV<7:0>: SYNC Fourth Byte Value bits These bits are to be set to configure the fourth byte of the SYNC word. SYNCV<7:0> = 00000000 (default) © 2010 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 SYNCV<15:8> Unimplemented bit, read as ‘0’ ...
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... Reserved (default the bit rate (refer to BRSREG (Register 2-4) for more information). Note: DS70622B-page 52 R/W-1 R/W-1 R/W-1 TXOPVAL<2:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared = 200 kHz (default Preliminary R/W-0 r — bit Bit is unknown © 2010 Microchip Technology Inc. ...
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... Reserved<1:0>: Reserved bits; do not use 00 = Reserved (default) © 2010 Microchip Technology Inc. R/W-1 R/W-1 R/W-1 CLKOFREQ<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared = 427 kHz (default Preliminary ...
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... R/W-0 R/W-0 PLDPLEN<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 NLADDR<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit Bit is unknown © 2010 Microchip Technology Inc. ...
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... Node Address Accepted; otherwise, rejected 00 = OFF (default) bit 0 STSCRCEN: Status Check CRC Enable bit This bit checks the status/result of the CRC of the current packet (read-only Not OK © 2010 Microchip Technology Inc. R/W-0 R/W-1 R/W-0 WHITEON CHKCRCEN ADDFIL<1:0> Unimplemented bit, read as ‘0’ ...
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... This bit indicate the read/write access for FIFO in Stand-by mode Read 0 = Write (default) bit 5-0 Reserved<5:0>: Reserved bits; do not use 00000 = Reserved (default) DS70622B-page — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2010 Microchip Technology Inc — — bit Bit is unknown ...
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TABLE 2-8: DETAILED CONFIGURATION/CONTROL/STATUS REGISTER MAP Register Function/ Register Register Name Bit 7 Parameter Address Type General 0x00 GCONREG 0x01 DMODREG 0x02 FDEVREG 0x03 BRSREG Reserved 0x04 FLTHREG 0x05 FIFOCREG 0x06 R1CREG 0x07 P1CREG 0x08 S1CREG 0x09 R2CREG 0x0A P2CREG ...
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... Microchip Technology Inc. Preliminary MRF89XA DS70622B-page 58 ...
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... The functional block diagram of the MRF89XA is illustrated in Figure 3-1. The functional operations of individual blocks are explained in subsequent sections. FIGURE 3-1: MRF89XA FUNCTIONAL BLOCK DIAGRAM PARS PA RFIO LNA LO1 RX OSC1 Frequency Synthesizer XO OSC2 © 2010 Microchip Technology Inc. Waveform I LO2 LO1 LO2 TX Q RSSI OOK Demod ...
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... When the TEST8 pin is driven high, an Note: current consumption can be seen on V Wait for Chip is ready from this point forward 10 ms Wait for Chip is ready from this point forward > 100 µ High-Z High-Z 1 Preliminary cannot be physically © 2010 Microchip Technology Inc. ...
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... PHASE-LOCKED LOOP (PLL) The frequency synthesizer of the MRF89XA is a fully integrated integer-N type PLL. The PLL circuit requires only five external components for the PLL loop filter and the VCO tank circuit. © 2010 Microchip Technology Inc. 3.2.4.1 PLL Requirements With integer-N ...
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... GCONREG (Register 2-1) • DMODREG (Register 2-2) • FLTHREG (Register 2-5) • OOKCREG (Register 2-22) Preliminary fsk xtaL 75 ∗ P × ------------ - + + × – dev xtaL 75 ∗ P × ------------ - + + – dev × – IF2 , ∗ P xtaL × IF2 ------------ - + – © 2010 Microchip Technology Inc. ...
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... Equation 3-6. EQUATION 3-6: f dev β • ≥ -------- - = © 2010 Microchip Technology Inc. For communication between a pair of MRF89XAs the should be at least 33 kHz to ensure a correct f dev operation on the receiver side. 3.3.4 SETTING IN OOK MODE f dev has no physical meaning in OOK Transmit mode. f ...
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... After power-up and with the Transmit registers enabled, the transmitter preloads the FIFO with preambles before sending the actual data based on the mode of operation. Figure 3-4 illustrates the PA Control Timing. 95% 95% t PARS t PARS PA_OUT t PA_OUT Preliminary © 2010 Microchip Technology Inc. ...
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... OPP the POLCFV<3:0> bits (PFCREG<7:4>), and F the upper 3 dB bandwidth of the filter whose offset, referenced given by BUTFILV<3:0> bits OPP (FILCREG<3:0>). © 2010 Microchip Technology Inc. 3.4.1 MRF89XA SECOND IF FILTER DETAILS FIGURE 3-5: Butterworth Low-Pass Filter for FSK OPP ...
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... EQUATION 3-10: Figure 3-11 illustrates an accurate overview of the filter bandwidth vs. setting. Preliminary Active Filter f requency f requency should be such that the modulated c drift over the operating • > 99%,fsk drifts © 2010 Microchip Technology Inc. ...
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... Microchip Technology Inc. Again function of the BUTFILV<3:0> bits described in Section 3.4.6 “Channel Filters Setting in OOK Mode”. 3.4.5 CHANNEL FILTERS SETTING IN FSK MODE , the 3dB cut-off frequency of the Butterworth filter f c used in FSK reception, is programmed through the BUTFILV< ...
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... I(t) and Q(t) signals (that is, the sec- ond Intermediate Frequency, IF2, of the receiver). Note that this equals f polyphase filter. Preliminary performing absolute RSSI Actual Theoretical parameter (as dev frequency deviation of the parameter (as dev , the center frequency of the o © 2010 Microchip Technology Inc. ...
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... RSSI IRQ TIMINGS 24 26 RSSIVAL<7:0> RIRQS © 2010 Microchip Technology Inc. The RSSI response versus the input signal is indepen- dent of the receiver filter bandwidth. However, in the absence of any input signal, the minimum value directly reflects upon the noise floor of the receiver, which is dependant on the filter bandwidth of the receiver ...
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... Threshold” that is programmed through the FTOVAL<7:0> bits (FLTHREG<7:0>). The default settings of the OOK demodulator lead to the performance stated in Section 5.0 “Electrical Characteristics”. Fixed 6dB difference Preliminary © 2010 Microchip Technology Inc. • f dev ≥ 2 ''Peak -6 dB'' Threshold ''Floor'' threshold defined by FTOVAL< ...
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... The bandwidth of the channel filters FIGURE 3-12: FLOOR THRESHOLD OPTIMIZATION Increment FTOVAL<7:0> © 2010 Microchip Technology Inc therefore important to note that the setting of the FTOVAL<7:0> bits will be application-dependant. The procedure shown in the flow chart in Figure 3-12 is recommended to optimize the FTOVAL<7:0> bits. ...
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... Equation 3-15 allows for the correct reception consecutive ‘0’s or ‘1’s. EQUATION 3-14: OOKATHC<1:0> EQUATION 3-15: OOKATHC<1:0> Preliminary © 2010 Microchip Technology Inc. BRVAL<6:0> ⇒ --------------------------------- - cutoff 8 π • BRVAL<6:0> ⇒ ...
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... If there is a difference in Bit Rate between TX and RX, the amount of adjacent bits at the same level © 2010 Microchip Technology Inc. DATA DCLK IRQ1 that the BitSync can withstand. It can be esti- mated as given in Equation 3-17 ...
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... One bit period delay is required after the ris- ing edge of TXDONE to ensure correct RF trans- mission of the last bit. In practice this may not require special care in the MCU software due to IRQ processing time. Preliminary © 2010 Microchip Technology Inc. ...
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... RX and Stand-by All the other interrupts through RSSI, SYNC, Payload, WRITEBYTE, DCLK, PLL Lock are handled through either of these interrupts discussed prior. © 2010 Microchip Technology Inc. 3.6.3 FIFO CLEARING Table 3-3 below summarizes the status of the FIFO when switching between different modes. ...
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... RSTHIREG (Register 2-16) • FILCREG (Register 2-17) • PFCREG (Register 2-18) • SYNCREG (Register 2-19) • RSTSREG (Register 2-21) • OOKCREG (Register 2-22) • SYNCV31REG (Register 2-23) • SYNCV23REG (Register 2-24) Bit N-1 = Bit N = SYNCVAL<0> SYNCVAL<0> Preliminary © 2010 Microchip Technology Inc. ...
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... TABLE 3-4: DATA OPERATION MODE SELECTION Data Operation Mode Continuous Buffered Packet © 2010 Microchip Technology Inc. 3.8.2 DATA OPERATION MODES The MRF89XA has three different data operation modes which can be selected by the user or programmer: • Continuous mode: Each bit transmitted or received is accessed in real time at the DATA pin ...
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... DATA and IRQ1 pins (pin 20 and 22). DATA is sampled on the rising edge of DCLK and updated on the falling edge as shown in Figure 3-19. Preliminary DATA IRQ0 IRQ1 (DCLK) SPI CSCON CONFIG SCK SDI SDO © 2010 Microchip Technology Inc. ...
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... IRQ1TX 0 (default) IRQ1 IRQ1 1 In Continuous mode, no interrupt is available in Stand-by mode. Note 1: Also refer the DMODE1:DMODE0 bits in the FTXRXIREG and FTPRIREG registers for details. 2: © 2010 Microchip Technology Inc. Data Mode Interrupt Type Continuous Output Continuous Output Continuous Output Continuous Output ...
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... Enables Sync word recognition X Defines Sync word size X Defines the error tolerance on Sync word recognition X Defines Sync word value X Defines Sync word value X Defines Sync word value X Defines Sync word value Preliminary packet bits on the DATA pin Description Continuous) © 2010 Microchip Technology Inc. ...
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... BUFFERED MODE BLOCK DIAGRAM RX Data SYNC Recognition TX Datapath © 2010 Microchip Technology Inc. 3.10.1 TX PROCESSING After entering TX in Buffered mode, the MRF89XA expects the host microcontroller to write to the FIFO, through the SPI data interface, all the data bytes to be transmitted (preamble, Sync word, payload). ...
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... FIFO through SPI data interface, causing an over- run Preliminary b9 b10 b11 b12 b13 b14 b15 XXX b9 b10 b11 b12 b13 b14 b15 b16 b15 b14 b13 b12 b11 b10 b9 b8 © 2010 Microchip Technology Inc. ...
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... The DATA pin (pin 20), which is unused in Note: Buffered mode, should be pulled- through a 100 kΩ resistor. Table 2-4, DD provides details about the MRF89XA pin configuration and chip mode. © 2010 Microchip Technology Inc. RX Interrupt Data Mode Interrupt Type Buffered Output Buffered Output ...
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... Wait for FIFO threshold interrupt (i.e., Sync word has been detected and FIFO has filled up to the defined threshold packet end Stand-by (SR’s content is lost). 5. Read packet byte from FIFO until FIFOEMPTY goes low (or correct number of bytes is read Sleep mode. Preliminary © 2010 Microchip Technology Inc. to FIFO threshold ...
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... RECOG. PACKET HANDLER TX Datapath © 2010 Microchip Technology Inc. Another important feature is the ability to fill and empty the FIFO in Stand-by mode, ensuring optimum power consumption and adding more flexibility for the soft- ware. Figure 3-25 shows the interface diagram during Packet Mode. ...
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... Preamble (1010...) • Sync word (Network ID) • Optional Address byte (Node ID) • Message data • Optional 2-bytes CRC checksum Optional DC free data coding CRC checksum calculation Address Message byte 0 to (FIFO size) bytes Payload/FIFO Preliminary © 2010 Microchip Technology Inc. CRC 2-bytes ...
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... Fields added by the packet handler in TX and processed and removed in RX Optional User provided fields which are part of the payload Message part of the payload © 2010 Microchip Technology Inc. A variable length packet frame format is illustrated in Figure 3-27, which contains the following fields: • ...
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... To disable this function the user should set the value of the PLDPLEN<6:0> bits to the value of the FIFO size selected. The received length byte, as part of the Note: payload, is not stripped off the packet and is made available in the FIFO. Preliminary © 2010 Microchip Technology Inc. ...
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... FIGURE 3-28: CRC POLYNOMIAL IMPLEMENTATION data input © 2010 Microchip Technology Inc. 3.11.3.4 CRC-Based The CRC check is enabled by setting the CHKCRCEN bit (PKTCREG<3>). This bit is used for checking the integrity of the message. A 16-bit CRC checksum is calculated on the payload part of the packet and is appended to the end of the transmitted message ...
Page 90
... Figure 3-31. The data is dewhitened on the receiver side by XORing with the same random sequence. Payload whitening/dewhitening is made transparent for the user, who still provides/retrieves NRZ data to/from the FIFO. BR Payload... Preliminary FIFO. See the Manchester ... ... ... © 2010 Microchip Technology Inc. ...
Page 91
... Interrupt Name Interrupts IRQ0TXST 0 (default) IRQ0 IRQ0 1 IRQ1TX 0 (default) IRQ1 IRQ1 1 Note: Also refer the DMODE1 and DMODE0 bits in the FTXRXIREG and FTPRIREG registers for details. © 2010 Microchip Technology Inc LFSR Polynomial = Transmit data RX Interrupt Data Mode Interrupt Type Packet ...
Page 92
... X X Enables CRC calculation/check — X Enables and defines address filtering X X Enables CRC Status check — X Enables FIFO autoclear if CRC failed X X Defines FIFO access in Stand-by mode Preliminary HOST MCU CONNECTIONS IN PACKET MODE ® PIC Microcontroller © 2010 Microchip Technology Inc. ...
Page 93
... Go to Stand-by mode. 5. Read payload byte from FIFO until FIFOEMPTY goes low. (FRWAXS = 1 Sleep mode. © 2010 Microchip Technology Inc. 3.11.8 ADDITIONAL INFORMATION TO HANDLE PACKET MODE If the number of bytes filled for transmission is greater than the actual length of the packet to be transmitted and IRQ0TXST = 1, the FIFO is cleared after the packet has been transmitted ...
Page 94
... SPLL = 1, it implies that the MRF89XA is ready to operate at the frequency indi- cated by the Ri/Pi/Si register set. 5: Program the CMOD bits (GCONREG 0x00 <7:5>) to ‘0b001 Standby mode. using the Preliminary and SYNCREG register, set . c transmit power using the Parameters, IRQ Parameters, © 2010 Microchip Technology Inc. ...
Page 95
... OK, the microcontrollers in sleeping field nodes can usually operate from internal low-accuracy R-C timers © 2010 Microchip Technology Inc. . Many host microcontrollers cannot be Note: operated from the MRF89XA buffered clock output if sleep cycling is planned ...
Page 96
... The registers associated with power-saving modes are: • GCONREG (Register 2-1) • DMODREG (Register 2-2) • FDEVREG (Register 2-3) • BRSREG (Register 2-4) • FTXRXIREG (Register 2-14) • FTPRIREG (Register 2-15) • CLKOUTREG (Register 2-28) Preliminary © 2010 Microchip Technology Inc. ...
Page 97
... SAW filter and antenna is illus- trated in Figure 4-1. This application design (that is, schematics and BOM) can be replicated in the final application board for optimum performance. FIGURE 4-1: APPLICATION CIRCUIT SCHEMATIC © 2010 Microchip Technology Inc. TEST3 SDO DD V CSDATA ...
Page 98
... SAW FILTER PLOT Figure 4-2 and Figure 4-3 illustrates the plots of the SAW filter used in the application circuit. The plots shown are representative. For exact specifications, refer to the SAW Filter manufacturer data sheet Preliminary © 2010 Microchip Technology Inc. ...
Page 99
... FIGURE 4-3: 915 MHz SAW FILTER PLOT 0 -10 -20 -30 -40 -50 -60 -70 -80 400 600 800 © 2010 Microchip Technology Inc. 1000 1200 1400 Frequency [MHz] 1000 1200 1400 Frequency [MHz] Preliminary MRF89XA 1600 1800 2000 1600 1800 2000 DS70622B-page 99 ...
Page 100
... As the PA and the LNA front-ends in the MRF89XA share the same input/output pin, they are internally matched to approximately 50Ω. Figure 4-4illustrates optimum load impedance of RFIO through an imped- ance chart. Pmax-1dB circle Max Power Zopt = 30 + j25Ω Preliminary © 2010 Microchip Technology Inc. ...
Page 101
... The external inductance is used to bias the PA. In Receive mode, both the PA and PA regulator are OFF and PARS is tied to ground. The RF choke induc- tor is then used to bias the LNA. © 2010 Microchip Technology Inc. 0.047 µF 100 nH 1Ω 1% SAW ...
Page 102
... Section 4.7 “Bill of Materi- als”). Minimum 9 10 xtal — 1 -15 -20 5 Preliminary line DD ramp start. The usage of DD line, hence follow DD Typical Maximum Units 12.800 15 MHz 15 16.5 pF — 100 Ohms — — +15 ppm — +20 ppm — 5 ppm © 2010 Microchip Technology Inc. ...
Page 103
... Murata Electronics North America Murata Electronics North America Murata Electronics North America Murata Electronics North America Johanson Technology Johanson Technology EPCOS Johanson Technology Johanson Technology Johanson Technology Johanson Technology Johanson Technology Vishay/Dale Yageo Yageo Yageo Microchip Technology Inc. © 2010 Microchip Technology Inc. ...
Page 104
... Murata Electronics North America Murata Electronics North America Murata Electronics North America Murata Electronics North America Johanson Technology Johanson Technology EPCOS Johanson Technology Johanson Technology Johanson Technology Johanson Technology Johanson Technology Vishay/Dale Yageo Yageo Yageo Microchip Technology Inc. © 2010 Microchip Technology Inc. ...
Page 105
... FIGURE 4-8: TWO BASIC COPPER FR4 LAYERS © 2010 Microchip Technology Inc. • Thorough decoupling on each power pin is beneficial for reducing in-band transceiver noise, particularly when this noise degrades performance. ...
Page 106
... MRF89XA FIGURE 4-9: FOUR BASIC COPPER FR4 LAYERS DS70622B-page 106 Signal Layout Dielectric Constant = 4.5 RF Ground Dielectric Constant = 4.5 Power Line Routing Dielectric Constant = 4.5 Ground Preliminary © 2010 Microchip Technology Inc. ...
Page 107
... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2010 Microchip Technology Inc. (except RFIO and V SS (1) ...
Page 108
... V — + 0.3 V — — 1.5 V — 1.5 V — DD Condition Sleep clock disabled, all blocks disabled (2) Oscillator and baseband enabled Frequency synthesizer running Output power = +10 dBm (1) Output power = +1 dBm — kHz 100 kHz, unless dev c © 2010 Microchip Technology Inc. ...
Page 109
... Oscillator Wake-up Time TSFS Frequency Synthesizer Wake-up Time; at most, 10 kHz away from the Target TSHOP Frequency Synthesizer Hop Time; at most, 10 kHz away from the Target Guaranteed by design and characterization Note 1: © 2010 Microchip Technology Inc. (1) Min Typ Max — — — ...
Page 110
... MHz step — — 1/f s From RX ready dev — 70 — dB Ranging from sensitivity Preliminary Condition = 100 kHz c = 200 kHz dev = 100 kHz c = 200 kHz kHz kHz 100 kHz 100 kHz kHz kHz 100 kHz 100 kHz o o © 2010 Microchip Technology Inc. ...
Page 111
... CSCON Rising to Falling Edge CSDAT Rising to Falling Edge Typical Values 25°C, V Note 1: A Negative current is defined as the current sourced by the pin Pin 10 (OSC1) and 11 (OSC2), maximum voltages of 1.8V can be applied. 3: © 2010 Microchip Technology Inc. (1) Min Typ Max — +12.5 — dBm — ...
Page 112
... Wait TSWRF Receiver is ready: - RSSI sampling is valid after Received data is valid Set MRF89XA in RX mode Wait for Receiver settling Set MRF89XA in FS mode Wait for PLL settling Preliminary MRF89XA can be put in Any other mode f dev period © 2010 Microchip Technology Inc. ...
Page 113
... Wait TSOSC Set MRF89XA in Stand-by mode Wait for OSC settling TSFS time can be improved by using the external lock detector pin as an external interrupt trigger. Note 1: © 2010 Microchip Technology Inc. TX Time Wait TSTR Wait TSFS Set MRF89XA in TX mode ...
Page 114
... IDDT Wait TSTWF Wait TS HOP 1. Set R2/P2/S2 2. Set MRF89XA in FS mode, change Frequency Band Select bits (FBS<1:0>) if needed, then switch from R1/P1/S1 to R2/P2/S2 Preliminary Time MRF89XA is now ready for data transmission Set MRF89XA back in TX mode © 2010 Microchip Technology Inc. ...
Page 115
... On channel 1 (R1/P1/S1 also possible to move from one channel to another without having to switch off the receiver. This method Note: is faster and overall draws more current. For timing information, refer to TSRHOP. © 2010 Microchip Technology Inc. Wait TSRWF MRF89XA is now ready for data reception ...
Page 116
... IDD IDDT 16 mA typ. @1 dBm IDDR 3.0 mA typ. Wait TSTWF MRF89XA mode DS70622B-page 116 Wait TSRWF Set MRF89XA in RX mode MRF89XA is now ready for data transmission Set MRF89XA in TX mode Preliminary Time MRF89XA is ready to receive data © 2010 Microchip Technology Inc. ...
Page 117
... Note: the ripple performance of the SAW filter (the nominal passband of the 869 MHz SAW filter is 868-870 MHz). The SAW filter ripple response is referenced to its insertion loss at 869 MHz and 915 MHz for each filter. © 2010 Microchip Technology Inc. 865 866 ...
Page 118
... DS70622B-page 118 6.0 5.0 4.0 3.0 2.0 1.0 0.0 -1 Drift [kHz] 6.0 5.0 4.0 3.0 2.0 1.0 0.0 -1.0 - Drift [kHz kHz typical. In OOK mode, “F3” is set at address c Preliminary 100 © 2010 Microchip Technology Inc. ...
Page 119
... FIGURE 5-11: OOK SENSITIVITY CHANGE VS 1.0 0 -1.0 -2.0 -3.0 -4.0 -5.0 -6.0 © 2010 Microchip Technology Inc. 150 200 of Active Filter [kHz 100 150 200 f -f [kHz Preliminary MRF89XA 250 300 250 300 350 ...
Page 120
... The sensitivity performance is very stable over the V Note: DS70622B-page 120 2.70 3.00 3.30 V [V] DD range, and the effect of high temperature is minimal. DD Preliminary 3.60 85°C 25°C 0°C -40°C © 2010 Microchip Technology Inc. ...
Page 121
... FIGURE 5-14: OOK SENSITIVITY VS. BR 2.0 1.5 1.0 0.5 0.0 1.5 4 -0.5 -1.0 -1.5 -2.0 -2.5 © 2010 Microchip Technology Inc Bit Rate [kbps] 6.5 9 11.5 Bit Rate [kbps] Preliminary MRF89XA 75 100 14 16.5 DS70622B-page 121 ...
Page 122
... DC cancellation process of the zero-IF architecture. In OOK mode, the polyphase filter efficiency is limited, thus limiting the adjacent channel rejection at 2xFo distance. DS70622B-page 122 -200 0 200 400 Offset [kHz -100 0 100 -10 -20 Offset [kHz] Preliminary 600 800 1000 200 300 © 2010 Microchip Technology Inc. ...
Page 123
... MHz band recommended that an appropriate SAW filter be implemented or that the SAW response is tuned by external matching. The SAW filter ripple references are the insertion loss of each SAW at 869 MHz and 915 MHz. © 2010 Microchip Technology Inc. 865 866 867 ...
Page 124
... TX Output Power (TXOPVAL<2:0>) [d] Pout ALL PA SETTINGS – 915 MHz 4567 TX Output Power (TXOPVAL<2:0>) [d]] Pout I DD Preliminary 28.00 26.00 24.00 22.00 20.00 18.00 16.00 14.00 12.00 10.00 7 30.0 28.0 26.0 24.0 22.0 20.0 18.0 16.0 14.0 12.0 10.0 © 2010 Microchip Technology Inc. ...
Page 125
... STABILITY OUT 1.0 0.5 0.0 2.1 2.4 -0.5 -1.0 -1.5 -2.0 The output power is not sensitive to the supply voltage, and it decreases slightly when temperature rises. © 2010 Microchip Technology Inc. 2.7 3.0 3.3 V [V] DD Preliminary MRF89XA 3.6 85ºC 25ºC -40ºC 0ºC ...
Page 126
... MRF89XA 5.4.10 TRANSMITTER SPECTRAL PURITY FIGURE 5-22: 869 MHz SPECTRAL PURITY DC-1 GHz FIGURE 5-23: 869 MHz SPECTRAL PURITY 1-6 GHz DS70622B-page 126 Preliminary © 2010 Microchip Technology Inc. ...
Page 127
... The OOK bit rate ranges form 1.56 to 16.7 kbps. For the lowest bit rates, a channel spacing around 200 kHz is achievable. FIGURE 5-24: OOK SPECTRUM – 2 kbps FIGURE 5-25: OOK SPECTRUM – 8 kbps © 2010 Microchip Technology Inc. Preliminary MRF89XA DS70622B-page 127 ...
Page 128
... MRF89XA FIGURE 5-26: OOK SPECTRUM – 16.7 kbps DS70622B-page 128 Preliminary © 2010 Microchip Technology Inc. ...
Page 129
... The default configuration of the MRF89XA yields the bandwidth visible on Figure 5-28. FIGURE 5-28: FSK – 25 KBPS – ±50 kHz Figure 5-28 illustrates the maximal bit rate and frequency deviation that can fit in the 868 to 868.6 MHz European sub-band. © 2010 Microchip Technology Inc. Preliminary MRF89XA DS70622B-page 129 ...
Page 130
... MRF89XA FIGURE 5-29: FSK – 40 KBPS – ±40 kHz DS70622B-page 130 Preliminary © 2010 Microchip Technology Inc. ...
Page 131
... Figure 5-32 provides graphs for I vs. Temperature DD and © 2010 Microchip Technology Inc. The MRF89XA can meet these constraints while transmitting at the maximum output power of the device, typically 10 dBm. The built-in whitening process details are described in Section 3.11.4.2 “Data Whitening”. ...
Page 132
FIGURE 5-32: I vs. Temperature and V DD Sleep Mode Current 1200 1000 800 600 400 200 0 2.1 2.4 2.7 3 VDD [V] FS Mode Current 2.00 1.80 1.60 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0.00 2.1 2.4 ...
Page 133
... PACKAGING INFORMATION 6.1 Package Details This section provides the technical details of the packages. © 2010 Microchip Technology Inc. Preliminary MRF89XA DS70622B-page 133 ...
Page 134
... MRF89XA NOTES: DS70622B-page 134 Preliminary © 2010 Microchip Technology Inc. ...
Page 135
... OOK RX FILTERS VS. BIT RATE Bit Rate kbps kHz 16.67 117 12.5 113 9.52 110 8 108 4.76 105 2.41 102 1.56 102 © 2010 Microchip Technology Inc. RX 3dB BW Fdev + BR/2 Programmed Hex kHz kHz FF 250 400 E9 166.7 250 D6 125 175 B5 100 150 A4 83 ...
Page 136
... This is the initial version of this document. Revision B (June 2010) Updates have been incorporated throughout the document, which required extensive revisions to all chapters. This version also includes minor typographical and formatting changes throughout the data sheet text. DS70622B-page 136 Preliminary © 2010 Microchip Technology Inc. ...
Page 137
... To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2010 Microchip Technology Inc. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • Distributor or Representative • ...
Page 138
... What deletions from the document could be made without affecting the overall usefulness there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS70622B-page 138 Total Pages Sent ________ FAX: (______) _________ - _________ N Literature Number: DS70622B Preliminary © 2010 Microchip Technology Inc. ...
Page 139
... IRQ Pins and Interrupts ...................................................... Generator ...................................................................... 17 Low Noise Amplifier (with First Mixer)................................. 15 M Memory Map ....................................................................... 28 Microchip Internet Web Site .............................................. 137 O OOK Receiver Setting......................................................... 22 © 2010 Microchip Technology Inc. P Packaging Details....................................................................... 133 Packaging Information ...................................................... 133 Phase-Locked Loop Architecture........................................ 17 Pin Descriptions.................................................................. 13 Pins CLKOUT ............................................................... 17, 23 DATA ...
Page 140
... Sensitivity Stability over Temperature and Voltage .. 120 Sensitivity vs. Bit Rate .............................................. 121 Sensitivity vs. LO Drift............................................... 118 Sensitivity vs. Receiver BW ...................................... 119 Transmitter Spectral Purity ....................................... 126 V Voltage Controlled Oscillator .............................................. 17 W Write Bytes Sequence ........................................................ 26 Write Register Sequence.................................................... 24 WWW Address ................................................................. 137 WWW, On-Line Support ....................................................... 5 Preliminary © 2010 Microchip Technology Inc. ...
Page 141
... MRF89XA: Ultra Low-Power, Integrated ISM Band Sub-GHz Transceiver Temperature I = -40ºC to +85ºC (Industrial) Range Package MQ = QFN (Quad Flat, No Lead Tape and Reel © 2010 Microchip Technology Inc. Example: XXX a) MRF89XA-I/MQ: Industrial temperature, QFN package. Pattern b) MRF89XAT-I/MQ: Industrial temperature, QFN package, tape and reel. Preliminary MRF89XA . DS70622B-page 141 ...
Page 142
... Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 Preliminary © 2010 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...