MRF89XAT-I/MQ Microchip Technology, MRF89XAT-I/MQ Datasheet - Page 92

• Manufacturer Part Number: MRF89XAT-I/MQ
• Description: RF ISM BAND TXRX 32 QFN
• Manufacturer: Microchip Technology
• Series: -r

Specifications of MRF89XAT-I/MQ

• Frequency: 863MHz ~ 870MHz, 902MHz ~ 928MHz, 950MHz ~ 960MHz
• Data Rate - Maximum: 200 kbps
• Modulation Or Protocol: FSK, OOK
• Applications: ISM
• Power - Output: 12.5dBm
• Sensitivity: -113dBm
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 3mA
• Current - Transmitting: 25mA
• Data Interface: PCB, Surface Mount
• Memory Size: *
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Rf Ic Case Style: QFN
• No. Of Pins: 32
• Svhc: No SVHC (20-Jun-2011)
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: MRF89XAT-I/MQTR

3.11.6
Depending on the application, some of the host
microcontroller connections may not be needed:
• IRQ0: If none of the relevant IRQ sources are
• IRQ1: If none of the relevant IRQ sources are
• SDO: If no read register access is needed and the
TABLE 3-13:
DS70622B-page 92
MRF89XA
DMODREG
FIFOCREG
FIFOCREG
FTXRXIREG
FTXRXIREG
FTXRXIREG
FTPRIREG
SYNCREG
SYNCREG
SYNCREG
SYNCV31REG
SYNCV23REG
SYNCV15REG
SYNCV07REG
PLOADREG
PLOADREG
NADDSREG
PKTCREG
PKTCREG
PKTCREG
PKTCREG
PKTCREG
PKTCREG
FCRCERG
FCRCERG
Note 1:
used. In this case, leave the pin floating.
used. In this case, leave the pin floating.
device is used in TX mode only. In this case, pull
up to V
Note:
Register Name
DD
Fixed format only.
HOST MICROCONTROLLER
INTERFACE CONNECTIONS IN
PACKET MODE
The DATA pin (pin 20), which is unused in
Packet mode, should be pulled-up to V
through a 100 kΩ resistor. Table 2-4, pro-
vides details about MRF89XA pin configu-
ration and chip mode.
through a 100 kΩ resistor.
CONFIGURATION REGISTERS RELATED TO DATA PROCESSING (ONLY) IN
PACKET MODE
DMODE0, DMODE1
FSIZE<1:0>
FTINT<5:0>
IRQ0RXS<1:0>
IRQ1RXS<1:0>
IRQ1TX
IRQ0TXST
SYNCREN
SYNCWSZ<1:0>
SYNCTEN<1:0>
SYNCV<31:24>
SYNCV<23:16>
SYNCV<15:8>
SYNCV<7:0>
MCHSTREN
PLDPLEN<6:0>
NLADDR<7:0>
PKTLENF
PRESIZE<1:0>
WHITEON
CRCEN
ADDFIL<1:0>
CRCSTSEN
ACFCRC
FRWAXS
Register Bits
X
TX
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
(1)
Preliminary
DD
RX
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Defines data operation mode ( Packet)
Defines FIFO size
Defines FIFO threshold
Defines IRQ0 source in RX & Stand-by modes
Defines IRQ1 source in RX & Stand-by modes
Defines IRQ1 source in TX mode
Defines IRQ0 source in TX mode
Enables Sync word recognition
Defines Sync word size
Defines the error tolerance on Sync word recognition
Defines Sync word value
Defines Sync word value
Defines Sync word value
Defines Sync word value
Enables Manchester encoding/decoding
Length in fixed format, max RX length in variable format
Defines node address for RX address filtering
Defines packet format (fixed or variable length)
Defines the size of preamble to be transmitted
Enables whitening/de-whitening process
Enables CRC calculation/check
Enables and defines address filtering
Enables CRC Status check
Enables FIFO autoclear if CRC failed
Defines FIFO access in Stand-by mode
FIGURE 3-32:
3.11.7
The data processing related registers are appropriately
configured as shown in Table 3-13. In this example we
assume CRC is enabled with autoclear on.
MRF89XA
PACKET MODE EXAMPLE
CSCON
CSDAT
IRQ0
IRQ1
SDO
SCK
Description
SDI
HOST MCU
CONNECTIONS IN
PACKET MODE
© 2010 Microchip Technology Inc.
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