MRF89XAT-I/MQ Microchip Technology, MRF89XAT-I/MQ Datasheet - Page 84

• Manufacturer Part Number: MRF89XAT-I/MQ
• Description: RF ISM BAND TXRX 32 QFN
• Manufacturer: Microchip Technology
• Series: -r

Specifications of MRF89XAT-I/MQ

• Frequency: 863MHz ~ 870MHz, 902MHz ~ 928MHz, 950MHz ~ 960MHz
• Data Rate - Maximum: 200 kbps
• Modulation Or Protocol: FSK, OOK
• Applications: ISM
• Power - Output: 12.5dBm
• Sensitivity: -113dBm
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 3mA
• Current - Transmitting: 25mA
• Data Interface: PCB, Surface Mount
• Memory Size: *
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Rf Ic Case Style: QFN
• No. Of Pins: 32
• Svhc: No SVHC (20-Jun-2011)
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: MRF89XAT-I/MQTR

TABLE 3-10:
TX Mode:
1.
2.
3.
4.
5.
DS70622B-page 84
MRF89XA
DMODREG
FIFOCREG
FIFOCREG
FTXRXIREG
FTXRXIREG
FTXRXIREG
FTPRIREG
FTPRIREG
FTPRIREG
SYNCREG
SYNCREG
SYNCREG
SYNCV31REG
SYNCV23REG
SYNCV15REG
SYNCV07REG
Register Name
Program TX start condition and IRQs: Start TX
when FIFO is not empty (IRQ0TXST = 1) and
IRQ1 mapped to TXDONE (IRQ1TX = 1).
Go to TX mode (and wait for TX to be ready, see
Figure 5-3).
Write packet bytes into FIFO. TX starts when the
first byte is written (IRQ0TXST = 1). Assump-
tion: The FIFO is being filled through the SPI
Data faster than being unfilled by SR.
Wait for TXDONE interrupt (+ 1 bit period).
Go to Sleep mode.
CONFIGURATION REGISTERS RELATED TO DATA PROCESSING (ONLY) IN
BUFFERED MODE
DMODE0, DMODE1
FSIZE<1:0>
FTINT<5:0>
IRQ0RXS<1:0>
IRQ1RXS<1:0>
IRQ1TX
IRQ0TXST
FIFOFM
FIFOFSC
SYNCREN
SYNCWSZ<1:0>
SYNCTEN<1:0>
SYNCV<31:24>
SYNCV<23:16>
SYNCV<15:8>
SYNCV<7:0>
Register Bits
TX
Preliminary
X
X
X
X
X
RX
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Defines data operation mode ( Buffered)
Defines FIFO size
Defines FIFO threshold
Defines IRQ0 source in RX mode
Defines IRQ1 source in RX mode
Defines IRQ1 source in TX mode
Defines IRQ0 source in TX mode
Defines FIFO filling method
Controls FIFO filling status
Enables Sync word recognition
Defines Sync word size
Defines the error tolerance on Sync word recognition
Defines Sync word value
Defines Sync word value
Defines Sync word value
Defines Sync word value
RX Mode:
1.
2.
3.
4.
5.
6.
Program RX/Stand-by interrupts: IRQ0 mapped
to FIFOEMPTY (IRQ0RXS<1:0> = 10) and
IRQ1
(IRQ1RXS<1:0> = 11). Configure FIFO thresh-
old to an appropriate value (for example, to
detect packet end, if its length is known).
Go to RX mode (note that RX is not ready imme-
diately, see Section 5.3.1 “Optimized Receive
Cycle” for more information).
Wait for FIFO threshold interrupt (i.e., Sync word
has been detected and FIFO has filled up to the
defined threshold).
If it is packet end, go to Stand-by (SR’s content
is lost).
Read packet byte from FIFO until FIFOEMPTY
goes low (or correct number of bytes is read).
Go to Sleep mode.
mapped
Description
© 2010 Microchip Technology Inc.
to
FIFO
threshold