MRF89XAT-I/MQ Microchip Technology, MRF89XAT-I/MQ Datasheet - Page 77
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MRF89XAT-I/MQ
Manufacturer Part Number
MRF89XAT-I/MQ
Description
RF ISM BAND TXRX 32 QFN
Manufacturer
Microchip Technology
Series
-r
Datasheet
1.MRF89XA-IMQ.pdf
(142 pages)
Specifications of MRF89XAT-I/MQ
Frequency
863MHz ~ 870MHz, 902MHz ~ 928MHz, 950MHz ~ 960MHz
Data Rate - Maximum
200 kbps
Modulation Or Protocol
FSK, OOK
Applications
ISM
Power - Output
12.5dBm
Sensitivity
-113dBm
Voltage - Supply
2.1 V ~ 3.6 V
Current - Receiving
3mA
Current - Transmitting
25mA
Data Interface
PCB, Surface Mount
Memory Size
*
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Rf Ic Case Style
QFN
No. Of Pins
32
Svhc
No SVHC (20-Jun-2011)
Rohs Compliant
Yes
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
MRF89XAT-I/MQTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MRF89XAT-I/MQ
Manufacturer:
MICROCHIP
Quantity:
12 000
3.8
3.8.1
The MRF89XA data processing blocks are as
illustrated in the Figure 3-16. Its role is to interface the
data to/from the modulator/demodulator and the host
microcontroller access points (SPI, Interrupts (IRQ0
and IRQ1), DATA pins). It also controls all the configu-
ration registers.
The circuit contains several control blocks which are
described in the following paragraphs.
The MRF89XA implements several data operation
modes, each with their own data path through the data
processing section. Depending on the data operation
mode selected, some control blocks are active while
others remain disabled.
FIGURE 3-16:
TABLE 3-4:
© 2010 Microchip Technology Inc.
Continuous
Buffered
Packet
Data Operation Mode
Data
Data Processing
DATA PROCESSING BLOCK
DIAGRAM
TX/RX
RX
TX
DATA OPERATION MODE SELECTION
Recognition
MRF89XA DATA PROCESSING BLOCK DIAGRAM
SYNC
Handler
Packet
DMODE1
0
0
1
MRF89XA
Preliminary
Control
(+SR)
FIFO
3.8.2
The MRF89XA has three different data operation
modes which can be selected by the user or
programmer:
• Continuous mode: Each bit transmitted or
• Buffered mode: Each byte transmitted or received
• Packet mode (recommended): User only pro-
received is accessed in real time at the DATA pin.
This mode may be used if adequate external sig-
nal processing is available.
is stored in a FIFO and accessed through the SPI
bus. The host microcontroller processing over-
head reduced significantly compared to Continu-
ous mode operation. The packet length is
unlimited.
vides/retrieves payload bytes to/from the FIFO.
The packet is automatically built with preamble,
Sync word, and optional CRC, DC free encoding
and the reverse operation is performed in recep-
tion. The host microcontroller processing over-
head is further reduced compared to Buffered
mode. The maximum payload length is limited to
the maximum FIFO limit of 64 bytes.
DMODE0
0
1
x
DATA OPERATION MODES
CONFIG
DATA
SPI
MRF89XA
FTXRXIREG
FTXRXIREG
FTXRXIREG
Register
DS70622B-page 77
SDO
CSDAT
SCK
SDI
DATA
IRQ1
IRQ0