MRF89XAT-I/MQ Microchip Technology, MRF89XAT-I/MQ Datasheet - Page 82

• Manufacturer Part Number: MRF89XAT-I/MQ
• Description: RF ISM BAND TXRX 32 QFN
• Manufacturer: Microchip Technology
• Series: -r

Specifications of MRF89XAT-I/MQ

• Frequency: 863MHz ~ 870MHz, 902MHz ~ 928MHz, 950MHz ~ 960MHz
• Data Rate - Maximum: 200 kbps
• Modulation Or Protocol: FSK, OOK
• Applications: ISM
• Power - Output: 12.5dBm
• Sensitivity: -113dBm
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 3mA
• Current - Transmitting: 25mA
• Data Interface: PCB, Surface Mount
• Memory Size: *
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Rf Ic Case Style: QFN
• No. Of Pins: 32
• Svhc: No SVHC (20-Jun-2011)
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: MRF89XAT-I/MQTR

FIGURE 3-22:
3.10.2
After entering RX in Buffered mode, the MRF89XA
requires the host microcontroller to get received data
from the FIFO. The FIFO will start being filled with
received bytes either when a Sync word has been
detected (in this case only the bytes following the Sync
word are filled into the FIFO) or when the FIFOFSC bit
(FPPRIREG<6>) is issued by the user depending on
the state of bit, FIFOFM (FTPRIREG<7>).
In Buffered mode, the packet length is not limited that
is, as long as FIFOFSC is set the received bytes are
shifted into the FIFO.
FIGURE 3-23:
DS70622B-page 82
MRF89XA
FIFO
15
FIFO
Data TX
(from SR)
Start condition
IRQ0TXST
TXDONE
0
FIFOFULL
FIFOEMPTY
Data RX
(to SR)
Start condition
(FIFOFM)
FIFOEMPTY
FIFOFULL
FOVRRUN
WRITEBYTE
15
0
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“noisy” data
RX PROCESSING
Preamble
TX PROCESSING IN BUFFERED MODE (FSIZE = 16, TXSTIRQ0 = 0))
RX PROCESSING IN BUFFERED MODE (FSIZE = 16, FIFOFM = 0)
XXX
SPI Data
from
Sync
b0
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b0
Preliminary
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The host microcontroller software must therefore man-
age the transfer of the FIFO contents by interrupt and
ensure reception of the correct number of bytes. In this
mode, even if the remote transmitter has stopped, the
demodulator will output random bits due to noise.
When the FIFO is full, the FIFOFULL IRQ (source) is
issued to alert the host microcontroller that at that time,
the FIFO can still be unfilled without data loss. If the
FIFO is not unfilled, after the SR is full (that is, eight bits
periods later) FOVRRUN is asserted and the SR’s con-
tent is lost.
Figure 3-23 illustrates RX processing with a 16 byte
FIFO size and FIFOFSC = 0. Note that in the example
of Section 3.10.5 “Buffered Mode Example”, the
host microcontroller does not retrieve any bytes from
the FIFO through SPI data interface, causing an over-
run.
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© 2010 Microchip Technology Inc.
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XXX
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