MRF89XAT-I/MQ Microchip Technology, MRF89XAT-I/MQ Datasheet - Page 85

• Manufacturer Part Number: MRF89XAT-I/MQ
• Description: RF ISM BAND TXRX 32 QFN
• Manufacturer: Microchip Technology
• Series: -r

Specifications of MRF89XAT-I/MQ

• Frequency: 863MHz ~ 870MHz, 902MHz ~ 928MHz, 950MHz ~ 960MHz
• Data Rate - Maximum: 200 kbps
• Modulation Or Protocol: FSK, OOK
• Applications: ISM
• Power - Output: 12.5dBm
• Sensitivity: -113dBm
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 3mA
• Current - Transmitting: 25mA
• Data Interface: PCB, Surface Mount
• Memory Size: *
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Rf Ic Case Style: QFN
• No. Of Pins: 32
• Svhc: No SVHC (20-Jun-2011)
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: MRF89XAT-I/MQTR

3.11
Similar to Buffered mode operation, in Packet mode the
NRZ data to/from the (de)modulator is not directly
accessed by the host microcontroller but is stored in
the FIFO and accessed through the SPI data interface.
The MRF89XA’s packet handler also performs several
packet oriented tasks such as Preamble and Sync
word generation, CRC calculation/check, DC scram-
bling
filtering. This simplifies the software still further and
reduces microcontroller overhead by performing these
repetitive tasks within the MRF89XA itself.
FIGURE 3-25:
© 2010 Microchip Technology Inc.
Data
(whitening/dewhitening
Packet Mode
Datapath
TX
RX
RECOG.
SYNC
PACKET MODE BLOCK DIAGRAM
of
HANDLER
PACKET
data),
MRF89XA
address
Preliminary
CONTROL
(+SR)
FIFO
Another important feature is the ability to fill and empty
the FIFO in Stand-by mode, ensuring optimum power
consumption and adding more flexibility for the soft-
ware. Figure 3-25 shows the interface diagram during
Packet Mode.
Note:
Bit Synchronizer and Sync word recogni-
tion are automatically enabled in Packet
mode.
CONFIG
DATA
SPI
MRF89XA
DS70622B-page 85
/CSCON
SCK
SDI
SDO
CSDAT
IRQ1
IRQ0