MC9S08GT16CFB Freescale Semiconductor, MC9S08GT16CFB Datasheet - Page 164

• Manufacturer Part Number: MC9S08GT16CFB
• Manufacturer: Freescale Semiconductor

Specifications of MC9S08GT16CFB

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 16KB
• Total Internal Ram Size: 1KB
• # I/os (max): 36
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.08V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Timer/PWM (TPM) Module
CHnF — Channel n Flag
CHnIE — Channel n Interrupt Enable
MSnB — Mode Select B for TPM Channel n
MSnA — Mode Select A for TPM Channel n
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When channel n is configured for input capture, this flag bit is set when an active edge occurs on the
channel n pin. When channel n is an output compare or edge-aligned PWM channel, CHnF is set when
the value in the TPM counter registers matches the value in the TPM channel n value registers. This
flag is seldom used with center-aligned PWMs because it is set every time the counter matches the
channel value register, which correspond to both edges of the active duty cycle period.
A corresponding interrupt is requested when CHnF is set and interrupts are enabled (CHnIE = 1). Clear
CHnF by reading TPMxCnSC while CHnF is set and then writing a 0 to CHnF. If another interrupt
request occurs before the clearing sequence is complete, the sequence is reset so CHnF would remain
set after the clear sequence was completed for the earlier CHnF. This is done so a CHnF interrupt
request cannot be lost by clearing a previous CHnF.
Reset clears the CHnF bit. Writing a 1 to CHnF has no effect.
This read/write bit enables interrupts from channel n. Reset clears the CHnIE bit.
When CPWMS = 0, MSnB = 1 configures TPM channel n for edge-aligned PWM mode. For a
summary of channel mode and setup controls, refer to
When CPWMS = 0 and MSnB = 0, MSnA configures TPM channel n for input capture mode or output
compare mode. Refer to
1 = Input capture or output compare event occurred on channel n.
0 = No input capture or output compare event occurred on channel n.
1 = Channel n interrupt requests enabled.
0 = Channel n interrupt requests disabled (use software polling).
Table 10-3
MC9S08GB/GT Data Sheet, Rev. 2.3
for a summary of channel mode and setup controls.
Table
10-3.
Freescale Semiconductor