MC9S08GT16CFB Freescale Semiconductor, MC9S08GT16CFB Datasheet - Page 181
MC9S08GT16CFB
Manufacturer Part Number
MC9S08GT16CFB
Description
Manufacturer
Freescale Semiconductor
Datasheet
1.MC9S08GT16CFB.pdf
(290 pages)
Specifications of MC9S08GT16CFB
Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
20MHz
Interface Type
SCI/SPI
Program Memory Type
Flash
Program Memory Size
16KB
Total Internal Ram Size
1KB
# I/os (max)
36
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2.08V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant
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RE — Receiver Enable
RWU — Receiver Wakeup Control
SBK — Send Break
11.10.4 SCI x Status Register 1 (SCIxS1)
This register has eight read-only status flags. Writes have no effect. Special software sequences (that do
not involve writing to this register) are used to clear these status flags.
TDRE — Transmit Data Register Empty Flag
Freescale Semiconductor
When the SCI receiver is off, the RxD1 pin reverts to being a general-purpose port I/O pin.
This bit can be written to 1 to place the SCI receiver in a standby state where it waits for automatic
hardware detection of a selected wakeup condition. The wakeup condition is either an idle line between
messages (WAKE = 0, idle-line wakeup), or a logic 1 in the most significant data bit in a character
(WAKE = 1, address-mark wakeup). Application software sets RWU and (normally) a selected
hardware condition automatically clears RWU. Refer to
Operation,”
Writing a 1 and then a 0 to SBK queues a break character in the transmit data stream. Additional break
characters of 10 or 11 bit times of logic 0 are queued as long as SBK = 1. Depending on the timing of
the set and clear of SBK relative to the information currently being transmitted, a second break
character may be queued before software clears SBK. Refer to
Queued
TDRE is set out of reset and when a transmit data value transfers from the transmit data buffer to the
transmit shifter, leaving room for a new character in the buffer. To clear TDRE, read SCIxS1 with
TDRE = 1 and then write to the SCI data register (SCIxD).
1 = Receiver on.
0 = Receiver off.
1 = SCI receiver in standby waiting for wakeup condition.
0 = Normal SCI receiver operation.
1 = Queue break character(s) to be sent.
0 = Normal transmitter operation.
1 = Transmit data register (buffer) empty.
0 = Transmit data register (buffer) full.
Idle,”
for more details.
for more details.
Reset:
Read:
Write:
TDRE
Bit 7
1
Figure 11-9. SCI x Status Register 1 (SCIxS1)
= Unimplemented or Reserved
MC9S08GB/GT Data Sheet, Rev. 2.3
TC
6
1
RDRF
5
0
IDLE
4
0
Section 11.6.3, “Receiver Wakeup
OR
3
0
Section 11.5.2, “Send Break and
NF
2
0
SCI Registers and Control Bits
FE
1
0
Bit 0
PF
0
181
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