MC9S08GT16CFB Freescale Semiconductor, MC9S08GT16CFB Datasheet - Page 165

• Manufacturer Part Number: MC9S08GT16CFB
• Manufacturer: Freescale Semiconductor

Specifications of MC9S08GT16CFB

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 16KB
• Total Internal Ram Size: 1KB
• # I/os (max): 36
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.08V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

If the associated port pin is not stable for at least two bus clock cycles before changing to input capture
mode, it is possible to get an unexpected indication of an edge trigger. Typically, a program would clear
status flags after changing channel configuration bits and before enabling channel interrupts or using the
status flags to avoid any unexpected behavior.
ELSnB:ELSnA — Edge/Level Select Bits
10.7.5
These read/write registers contain the captured TPM counter value of the input capture function or the
output compare value for the output compare or PWM functions. The channel value registers are cleared
by reset.
Freescale Semiconductor
CPWMS
Depending on the operating mode for the timer channel as set by CPWMS:MSnB:MSnA and shown
in
the level that will be driven in response to an output compare match, or select the polarity of the PWM
output.
Setting ELSnB:ELSnA to 0:0 configures the related timer pin as a general-purpose I/O pin unrelated
to any timer channel functions. This function is typically used to temporarily disable an input capture
channel or to make the timer pin available as a general-purpose I/O pin when the associated timer
channel is set up as a software timer that does not require the use of a pin. This is also the setting
required for channel 0 when the TPMxCH0 pin is used as an external clock input.
X
0
1
Table
Timer x Channel Value Registers (TPMxCnVH:TPMxCnVL)
10-3, these bits select the polarity of the input edge that triggers an input capture event, select
MSnB:MSnA
XX
XX
1X
00
01
ELSnB:ELSnA
Table 10-3. Mode, Edge, and Level Selection
X1
X1
00
01
10
11
00
01
10
11
10
10
MC9S08GB/GT Data Sheet, Rev. 2.3
Pin not used for TPM channel; use as an external clock for the TPM or
revert to general-purpose I/O
Output compare
Center-aligned
Input capture
Edge-aligned
Mode
PWM
PWM
Capture on rising edge only
Capture on falling edge only
Capture on rising or falling edge
Software compare only
Toggle output on compare
Clear output on compare
Set output on compare
High-true pulses (clear output on compare)
Low-true pulses (set output on compare)
High-true pulses (clear output on compare-up)
Low-true pulses (set output on compare-up)
Configuration
TPM Registers and Control Bits
165