MC9S08GT16CFB Freescale Semiconductor, MC9S08GT16CFB Datasheet - Page 90

• Manufacturer Part Number: MC9S08GT16CFB
• Manufacturer: Freescale Semiconductor

Specifications of MC9S08GT16CFB

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 16KB
• Total Internal Ram Size: 1KB
• # I/os (max): 36
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.08V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Chapter 6 Parallel Input/Output
PTDDn — Port D Data Register Bit n (n = 0–7)
PTDPEn — Pullup Enable for Port D Bit n (n = 0–7)
PTDSEn — Slew Rate Control Enable for Port D Bit n (n = 0–7)
PTDDDn — Data Direction for Port D Bit n (n = 0–7)
6.6.5
Port E includes eight general-purpose I/O pins that share with the SCI1 and SPI modules. Port E pins used
as general-purpose I/O pins are controlled by the port E data (PTED), data direction (PTEDD), pullup
enable (PTEPE), and slew rate control (PTESE) registers.
If the SCI1 takes control of a port E pin, the corresponding PTEDD bit is ignored. PTESE can be used to
provide slew rate on the SCI1 transmit pin, TxD1. PTEPE can be used, provided the corresponding
PTEDD bit is 0, to provide a pullup device on the SCI1 receive pin, RxD1.
If the SPI takes control of a port E pin, the corresponding PTEDD bit is ignored. PTESE can be used to
provide slew rate on the SPI serial output pin (MOSI1 or MISO1) and serial clock pin (SPSCK1)
depending on the SPI operational mode. PTEPE can be used, provided the corresponding PTEDD bit is 0,
to provide a pullup device on the SPI serial input pins (MOSI1 or MISO1) and slave select pin (SS1)
depending on the SPI operational mode.
Reads of PTED will return the logic value of the corresponding pin, provided PTEDD is 0.
90
For port D pins that are inputs, reads return the logic level on the pin. For port D pins that are
configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port D pins that are configured as outputs, the logic
level is driven out the corresponding MCU pin.
Reset forces PTDD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
For port D pins that are inputs, these read/write control bits determine whether internal pullup devices
are enabled. For port D pins that are configured as outputs, these bits are ignored and the internal pullup
devices are disabled.
For port D pins that are outputs, these read/write control bits determine whether the slew rate
controlled outputs are enabled. For port D pins that are configured as inputs, these bits are ignored.
These read/write bits control the direction of port D pins and what is read for PTDD reads.
1 = Internal pullup device enabled.
0 = Internal pullup device disabled.
1 = Slew rate control enabled.
0 = Slew rate control disabled.
1 = Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn.
0 = Input (output driver disabled) and reads return the pin value.
Port E Registers (PTED, PTEPE, PTESE, and PTEDD)
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor