MC9S08GT16CFB Freescale Semiconductor, MC9S08GT16CFB Datasheet - Page 30

• Manufacturer Part Number: MC9S08GT16CFB
• Manufacturer: Freescale Semiconductor

Specifications of MC9S08GT16CFB

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 16KB
• Total Internal Ram Size: 1KB
• # I/os (max): 36
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.08V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Chapter 2 Pins and Connections
For information about controlling these pins as general-purpose I/O pins, see
Input/Output.” For information about how and when on-chip peripheral systems use these pins, refer to the
appropriate section from
When an on-chip peripheral system is controlling a pin, data direction control bits still determine what is
read from port data registers even though the peripheral module controls the pin direction by controlling
the enable for the pin’s output buffer. See
Pullup enable bits for each input pin control whether on-chip pullup devices are enabled whenever the pin
is acting as an input even if it is being controlled by an on-chip peripheral module. When the PTA7–PTA4
pins are controlled by the KBI module and are configured for rising-edge/high-level sensitivity, the pullup
enable control bits enable pulldown devices rather than pullup devices. Similarly, when IRQ is configured
30
1
PTA7–PTA0
PTB7–PTB0
PTC7–PTC4
PTC3–PTC2
PTC1–PTC0
PTD7–PTD3
PTD2–PTD0
PTE7–PTE6
PTE5
PTE4
PTE3
PTE2
PTE1–PTE0
PTF7–PTF0
PTG7–PTG3
PTG2–PTG1
PTG0
See this section for information about modules that share these pins.
Port Pins
To avoid extra current drain from floating input pins, the reset initialization
routine in the application program should either enable on-chip pullup
devices or change the direction of unused pins to outputs so the pins do not
float.
KBI1P7–KBI1P0
AD1P7–AD1P0
SCL1–SDA1
RxD2–TxD2
TPM2CH4–
TPM1CH2–
SPSCK1
MISO1
MOSI1
SS1
RxD1–TxD1
EXTAL–XTAL
BKGD/MS
TPM2CH0
TPM1CH0
Alternate
Function
Table
—
—
—
—
2-1.
Table 2-1. Pin Sharing References
MC9S08GB/GT Data Sheet, Rev. 2.3
Chapter 2, “Pins and Connections”
Chapter 14, “Analog-to-Digital Converter (ATD) Module”
Chapter 6, “Parallel Input/Output”
Chapter 13, “Inter-Integrated Circuit (IIC) Module”
Chapter 11, “Serial Communications Interface (SCI) Module”
Chapter 10, “Timer/PWM (TPM) Module”
Chapter 10, “Timer/PWM (TPM) Module”
Chapter 6, “Parallel Input/Output”
Chapter 12, “Serial Peripheral Interface (SPI) Module”
Chapter 11, “Serial Communications Interface (SCI) Module”
Chapter 6, “Parallel Input/Output”
Chapter 6, “Parallel Input/Output”
Chapter 7, “Internal Clock Generator (ICG) Module”
Chapter 15, “Development Support”
Chapter 6, “Parallel
NOTE
Input/Output” for details.
Reference
1
Chapter 6, “Parallel
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