MC9S08GT16CFB Freescale Semiconductor, MC9S08GT16CFB Datasheet - Page 69

• Manufacturer Part Number: MC9S08GT16CFB
• Manufacturer: Freescale Semiconductor

Specifications of MC9S08GT16CFB

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 16KB
• Total Internal Ram Size: 1KB
• # I/os (max): 36
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.08V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

IRQPE — IRQ Pin Enable
IRQF — IRQ Flag
IRQACK — IRQ Acknowledge
IRQIE — IRQ Interrupt Enable
IRQMOD — IRQ Detection Mode
5.8.2
This register includes six read-only status flags to indicate the source of the most recent reset. When a
debug host forces reset by writing 1 to BDFR in the SBDFR register, none of the status bits in SRS will be
set. Writing any value to this register address clears the COP watchdog timer without affecting the contents
of this register. The reset state of these bits depends on what caused the MCU to reset.
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This read/write control bit enables the IRQ pin function. When this bit is set, the IRQ pin can be used
as an interrupt request. Also, when this bit is set, either an internal pull-up or an internal pull-down
resistor is enabled depending on the state of the IRQMOD bit.
This read-only status bit indicates when an interrupt request event has occurred.
This write-only bit is used to acknowledge interrupt request events (write 1 to clear IRQF). Writing 0
has no meaning or effect. Reads always return 0. If edge-and-level detection is selected
(IRQMOD = 1), IRQF cannot be cleared while the IRQ pin remains at its asserted level.
This read/write control bit determines whether IRQ events generate a hardware interrupt request.
This read/write control bit selects either edge-only detection or edge-and-level detection. The
IRQEDG control bit determines the polarity of edges and levels that are detected as interrupt request
events. See
1 = IRQ pin function is enabled.
0 = IRQ pin function is disabled.
1 = IRQ event detected.
0 = No IRQ request.
1 = Hardware interrupt requested whenever IRQF = 1.
0 = Hardware interrupt requests from IRQF disabled (use polling).
1 = IRQ event on falling edges and low levels or on rising edges and high levels.
0 = IRQ event on falling edges or rising edges only.
System Reset Status Register (SRS)
Section 5.5.2.2, “Edge and Level
MC9S08GB/GT Data Sheet, Rev. 2.3
Sensitivity”
Reset, Interrupt, and System Control Registers and Control Bits
for more details.
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