CYNSE70256-66BHC Cypress Semiconductor Corp, CYNSE70256-66BHC Datasheet - Page 11

• Manufacturer Part Number: CYNSE70256-66BHC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70256-66BHC

• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Table 4-1. CYNSE70256 Signal Description (continued)
Document #: 38-02035 Rev. *E
SRAM Interface
Cascade Interface
HIGH_SPEED
SADR[23:0]
FULO[1:0]
Pin Name
BHO[2:0]
FULI[6:0]
DQ[71:0]
LHO[1:0]
BHI[2:0]
LHI[6:0]
ACK
EOT
ALE_L
WE_L
OE_L
CE_L
FULL
SSV
SSF
[2]
[2]
Type
Pin
I/O
O
O
O
O
T
T
T
T
T
T
T
T
T
I
I
I
I
[1]
Address/Data Bus
register, data, and mask array operations. It carries the compare data during Search
operations. It also carries the SRAM address during SRAM PIO accesses.
Read Acknowledge
register, data, and mask array Read operations, or that the data is available on the SRAM
data bus during SRAM Read operations.
End of Transfer
during Read or Write burst operations.
Search Successful Flag
winner in a Search operation.
Search Successful Flag Valid
High Speed
well as forward device compatibility.
SRAM Address
associative data. See Table 12-1 for the details of the generated SRAM address. In a
database of multiple CYNSE70256s, each corresponding SADR bit from all cascaded
devices must be connected.
SRAM Chip Enable
of multiple CYNSE70256s, CE_L of all cascaded devices must be connected. This signal
is then driven by only one of the devices.
SRAM Write Enable
of multiple CYNSE70256s, WE_L of all cascaded devices must be connected. This signal
is then driven by only one of the devices.
SRAM Output Enable
last device drives this signal (with the LRAM bit set).
Address Latch Enable
address bus. In a database of multiple CYNSE70256s, the ALE_L of all cascaded devices
must be connected. This signal is then driven by only one of the devices.
Local Hit In
this bus is connected to the LHO[1] or LHO[0] of each of the upstream devices in a block.
All unused LHI pins are connected to a logic 0. For more information, see Section 11.0,
“Depth Cascading,” on page 84. LHI[0] stays unconnected.
Local Hit Out
up to four downstream devices in a block totalling up to four). For more information, see
Section 11.0, “Depth Cascading,” on page 84.
Block Hit In
device. In a four-block system, the last block can contain only seven devices because the
identification code 11111 is used for broadcast access.
Block Hit Out
inputs of the devices in the downstream blocks.
Full In
to generate the FULL flag for the depth-cascaded block. FULI[0] stays unconnected.
Full Out
devices in a depth-cascaded table. Bit[0] in the data array indicates whether the entry is
full (1) or empty (0). This signal is asserted if all bits in the data array are 1s. (Refer to
Section 11.0, “Depth Cascading,” on page 84, for information on how to generate the
FULL flag.)
Full Flag
devices is full.
. Each signal in this bus is connected to FULO[0] or FULO[1] of an upstream device
. Both of these signals must be connected to the FULI of up to four downstream
. When asserted, this signal indicates that the table of multiple depth-cascaded
. These pins depth-cascade the device to form a larger table. One signal of
. This pin must be connected to ground (V
. Inputs from the previous block BHO[2:0] are tied to BHI[2:0] of the current
. The LHO[1] and the LHO[0] are connected to one input on the LHI bus (from
. These outputs from the last device in a block are connected to the BHI[2:0]
. This bus contains address lines to access off-chip SRAMs that contain
. This signal indicates the end of burst transfer to the data or mask array
. This signal carries the Read and Write address and data during
. This is the chip-enable (CE) control for external SRAMs. In a database
. This signal indicates that valid data is available on the DQ bus during
. This is the Write-enable control for external SRAMs. In a database
. This is the output-enable (OE) control for external SRAMs. Only the
. When this signal is LOW, the addresses are valid on the SRAM
. When asserted, this signal indicates that the device is the global
. When asserted, this signal qualifies the SSF signal.
Pin Description
SS
). It is provided for backward as
CYNSE70256
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