CYNSE70256-66BHC Cypress Semiconductor Corp, CYNSE70256-66BHC Datasheet - Page 29

• Manufacturer Part Number: CYNSE70256-66BHC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70256-66BHC

• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

command cycle B) in each of the four devices. In the ×72 configuration, only the even comparand register can subsequently be
used by the Learn command in one of the devices (the first non-full device only). The word K (presented on the DQ bus in both
cycles A and B of the command) is compared with each entry in the table, starting at location 0. The first matching entry’s location
address L is the winning address that is driven as part of the SRAM address on the SADR[23:0] lines (see Section 12.0, “SRAM
Addressing,” on page 86). The global winning device will drive the bus in a specific cycle. On a global miss cycle, the device with
LRAM = 1 (default driving device for the SRAM bus) and LDEV = 1 (default driving device for SSF and SSV signals) will be the
default driver for such missed cycles.
The Search command is a pipelined operation and executes a Search at half the rate of the frequency of CLK2X for 72-bit
searches in ×72-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 72-bit Search command
cycle (two CLK2X cycles) is shown in Table 10-11.
Table 10-11. Search Latency from Instruction to SRAM Access Cycle
The latency of the Search from command to SRAM access cycle is 5 for up to four devices in the table (TLSZ = 01). SSV and
SSF also shift further to the right for different values of HLAT, as specified in Table 10-12.
Table 10-12. Shift of SSF and SSV from SADR
10.6.2
The hardware diagram of the Search subsystem of fifteen devices is shown in Figure 10-10. Each of the four blocks in the diagram
represents four CYNSE70256 devices (except the last, which has three devices). The diagram for a block of four devices is shown
in Figure 10-11. The following are the parameters programmed into the fifteen devices.
Document #: 38-02035 Rev. *E
Number of Devices
72-bit Search on Tables Configured as ×72 using up to Fifteen CYNSE70256 Devices
1–15 (TLSZ = 10)
1–4 (TLSZ = 01)
Will be same in each two banks of the four
HLAT
000
001
010
100
101
011
110
111
Must be same in each of the banks
Comparand Register (Odd)
Comparand Register (Even)
each of the four devices
71
devices
K
K
Figure 10-9. ×72 Table with Four Devices
0
Max Table Size
1920K × 72 bits
512K × 72 bits
Location
address
524,287
L
0
1
2
3
CFG = 0000000000000000
71
71
(72-bit configuration)
Number of CLK Cycles
GMR
K
0
1
2
3
4
5
6
7
0
0
(First matching entry)
Latency in CLK Cycles
5
6
CYNSE70256
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