CYNSE70256-66BHC Cypress Semiconductor Corp, CYNSE70256-66BHC Datasheet - Page 89

• Manufacturer Part Number: CYNSE70256-66BHC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70256-66BHC

• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

12.3
The following explains the SRAM Read operation accomplished through a table of up to fifteen devices, using the following
parameter: TLSZ = 10. The hardware diagram is shown in Figure 12-4. The following assumes that SRAM access is being
accomplished through CYNSE70256 device number 0, and that device number 0 is the selected device. Figure 12-5 and
Figure 12-6 show the timing diagrams for device number 0 and device number 14, respectively.
At the end of cycle 10, the selected device floats ACK in a three-state condition.
Document #: 38-02035 Rev. *E
• Cycle 1A: The host ASIC applies the Read instruction to CMD[1:0] using CMDV = 1. The DQ bus supplies the address, with
• Cycle 1B: The host ASIC continues to apply the Read instruction to CMD[1:0], using CMDV = 1. The DQ bus supplies the
• Cycle 2: The host ASIC floats DQ[71:0] to a three-state condition.
• Cycle 3: The host ASIC keeps DQ[71:0] in a three-state condition.
• Cycle 4: The selected device starts to drive DQ[71:0].
• Cycles 5 to 6: The selected device continues to drive DQ[71:0].
• Cycle 7: The selected device continues to drive DQ[71:0], and drives an SRAM Read cycle.
• Cycle 8: The selected device drives ACL from Z to LOW.
• Cycle 9: The selected device drives ACK to HIGH.
• Cycle 10: The selected device drives ACK from HIGH to LOW.
DQ[20:19] set to 10, to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21]
lines. During this cycle, the host ASIC also supplies SADR[23:21] on CMD[8:6].
address, with DQ[20:19] set to 10, to select the SRAM address.
SRAM Read with a Table of up to Fifteen Devices
DQ[71:0]
CMD[10:0], CMDV
SSF, SSV
Figure 12-4. Hardware Diagram of Fifteen Devices Using Four Blocks
BHO[2]
BHO[2]
BHI[2]
BHO[2]
BHO[2]
Block of 8 CYNSE70256s Block 2
Block of 7 CYNSE70256s Block 3
Block of 8 CYNSE70256s Block 0
Block of 8 CYNSE70256s Block 1
BHI[2]
BHI[2]
BHI[2]
(devices 12–14)
(devices 8–11)
(devices 0–3)
(devices 4–7)
BHO[1]
BHO[1]
BHI[1]
BHO[1]
BHO[1]
BHI[1]
BHI[1]
BHI[1]
BHO[0]
BHO[0]
BHO[0]
BHO[0]
BHI[0]
BHI[0]
BHI[0]
BHI[0]
GND
GND
GND
SRAM
CYNSE70256
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