CYNSE70256-66BHC Cypress Semiconductor Corp, CYNSE70256-66BHC Datasheet - Page 15

• Manufacturer Part Number: CYNSE70256-66BHC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70256-66BHC

• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Table 7-2. Search Successful Register Description
7.4
Table 7-3 describes the command registers’ fields for each of the two banks; Bank 0 and Bank 1.
Table 7-3. Command Register Description
Document #: 38-02035 Rev. *E
LRAM
SRST
DEVE
LDEV
TLSZ
HLAT
Field
INDEX
VALID
Field
–
–
Command Register
Range Initial Value
[3:2]
[6:4]
[0]
[1]
[7]
[8]
[30:16]
[71:32]
Range
[15:0]
[31]
000
01
0
0
0
0
Software Reset
it generates a reset pulse lasting for eight CLK cycles. This bit automatically resets to a 0 after
the reset has completed.
Device Enable
SSV signals in a three-state condition and forces the cascade interface output signals LHO[1:0]
and BHO[2:0] to 0. It also keeps the DQ bus in input mode. The purpose of this bit is to make
sure that there are no bus contentions when the devices power up in the system.
Table Size
size. This field affects the pipeline latency of the Search and Learn operations as well as the
Read and Write accesses to the SRAM (SADR[23:0], CE_L, OE_L, WE_L, ALE_L, SSV, SSF,
and ACK). Once programmed, the Search latency stays constant.
Latency in number of CLK cycles with HIGH_SPEED LOW:
01: Up to four devices
10: Up to fifteen devices
11: Reserved.
Latency of Hit Signals
and ACK signal during SRAM Read access by the following number of CLK cycles.
000: 0
001: 1
010: 2
011: 3
Last Device in the Cascade
table and is the default driver for the SSF and SSV signals. In the event of a Search failure, the
bank with this device with this bit set drives the hit signals as follows: SSF = 0, SSV = 1. During
non-Search cycles, the device with this bit set drives the signals as follows: SSF = 0, SSV = 0.
Last Device on the SRAM Bus
in the depth-cascaded table and is the default driver for the SADR, CE_L, WE_L, and ALE_L
signals. In cycles where no CYNSE70256 device in a depth-cascaded table drives these
signals, this drives the signals as follows: SADR = 23’hFFFFFF, CE_L = 1, WE_L = 1, and
ALE_L = 1. OE_L is always driven by the device for which this bit is set.
Initial Value
. The host ASIC must program this field to configure each bank into a table of a certain
X
0
0
0
111: 7.
100: 4
101: 5
110: 6
. If 0, it keeps the SRAM bus (SADR, WE_L, CE_L, OE_L and ALE_L), SSF, and
. If 1, this bit resets the bank with the same effect as a hardware reset. Internally,
. This field adds further latency to the SSF and SSV signals during Search,
Index
occurs. The device updates this field only when the search is successful.
If a hit occurs in a 144-bit entry-size quadrant, the least-significant bit (LSB)
is 0. If a hit occurs in a 288-bit entry-size quadrant, the two LSBs are 00.
This index updates if the device is either a local or global winner in
a Search operation.
Reserved
Valid
of the device that is a global winner in a match sets this bit to 1. This bit
updates only when the device is a global winner in a Search operation.
Reserved
. When set, this is the last bank of the last device in the depth-cascaded
. During Search operation in a depth-cascaded configuration, this ban
. This is the address of the 72-bit entry where a successful search
. When set, this is the last bank of the last device on the SRAM bus
.
.
5
6
Description
Description
CYNSE70256
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