CYNSE70256-66BHC Cypress Semiconductor Corp, CYNSE70256-66BHC Datasheet - Page 61

• Manufacturer Part Number: CYNSE70256-66BHC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70256-66BHC

• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

The 144-bit word K that is presented on the DQ bus in cycles A and B of the command is also stored in the even and odd
comparand registers specified by the comparand register index in command cycle B. In ×144 configurations, the even and odd
comparand registers can subsequently be used by the Learn command in only the first non-full device.
The Search command is a pipelined operation. It executes a Search at half the rate of the frequency of CLK2X for 144-bit searches
in ×144-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 144-bit Search command cycle
(two CLK2X cycles) is shown in Table 10-20.
Table 10-20. Search Latency from Instruction to SRAM Access Cycle
Search latency from command to the SRAM access cycle is 6 for 1–15 devices in the table and TLSZ = 10. In addition, SSV and
SSF shift further to the right for different values of HLAT, as specified in Table 10-21.
Table 10-21. Shift of SSF and SSV from SADR
10.6.5
The hardware diagram of the Search subsystem of four devices is shown in Figure 10-43. The following are the parameters
programmed into the four devices.
Notes:
Document #: 38-02035 Rev. *E
18. The Learn command is supported for only one of the blocks consisting of up to four devices in a depth-cascaded table of more than one block. The word K that
19. During 144-bit searches of 144-bit-configured tables, the Search hit will always be at an even address.
20. All four devices must be programmed with the same values of TLSZ and HLAT. Only the last bank of the last device in the table must be programmed with
• First seven devices (devices 0–6, Bank 0 and 1): CFG = 1010101010101010, TLSZ = 01, HLAT = 000, LRAM = 0, and LDEV = 0.
• Fourth device (device 7, Bank 0): CFG = 1010101010101010, TLSZ = 01, HLAT = 000, LRAM = 0, and LDEV = 0.
• Fourth device (device 7, Bank 1): CFG = 1010101010101010, TLSZ = 01, HLAT = 000, LRAM = 1, and LDEV = 1.
Number of Devices
is presented on the DQ bus in cycles A and B of the command is compared with each entry in the table, starting at location 0. The first matching entry’s location
address L is the winning address that is driven as part of the SRAM address on the SADR[23:0] lines (see Section 12.0, “SRAM Addressing,” on page 86). The
global winning device will drive the bus in a specific cycle. On global miss cycles the device with LRAM = 1 (the default driving device for the SRAM bus) and
LDEV = 1 (the default driving device for SSF and SSV signals) will be the default driver for such missed cycles.
LRAM = 1 and LDEV = 1 (device number 3 in this case).
1–14 (TLSZ = 10)
1–4 (TLSZ = 01)
Will be same in each of banks of each the 15 devices
288-bit Search on ×288-configured Tables using up to Four CYNSE70256 Devices
Must be same in each bank of each of the 15
HLAT
000
001
010
100
101
011
110
111
Comparand Register (odd)
Comparand Register (even)
71
devices
Figure 10-42. ×144 Table with Fifteen Devices
A
Max Table Size
256K × 144 bits
960K × 144 bits
B
0
1966078
Location
address
GMR
L
0
2
4
6
K
CFG = 0101010101010101
143
143
Number of CLK Cycles
Even
A
0
1
2
3
4
5
6
7
Odd
B
Latency in CLK Cycles
0
0
(First matching entry)
(144-bit configuration)
5
6
[18, 19]
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