CYNSE70256-66BHC Cypress Semiconductor Corp, CYNSE70256-66BHC Datasheet - Page 19

• Manufacturer Part Number: CYNSE70256-66BHC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70256-66BHC

• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

9.0
Figure 9-1 shows CYNSE70256 data and mask array addressing for both Bank 0 and Bank 1.
10.0
A master device such as an ASIC controller issues commands to the CYNSE70256 device using the CMDV signal and the
command bus. The following subsections describe the operation of these commands.
10.1
The CYNSE70256 device implements four basic commands, as shown in Table 10-1. The command code must be presented to
CMD[1:0] while keeping the CMDV signal HIGH for two CLK2X cycles (cycles A and B) when the CLK_MODE pin is LOW. In
CLK2X mode, the controller ASIC must align the instructions using the PHS_L signal. The command code must be presented to
CMD[1:0] while keeping the CMDV signal HIGH for one CLK1X cycle when the CLK_MODE pin is HIGH. In CLK1X mode the
HIGH phase is cycle A and the LOW phase is cycle B. The CMD[10:2] field passes command parameters in cycles A and B.
Table 10-1. Command Codes
10.2
Table 10-2 lists the command bus fields that contain the CYNSE70256 command parameters and their respective cycles. Each
command is described separately in the subsections that follow.
Document #: 38-02035 Rev. *E
Command Code
CFG = 0000000000000000 (Bank 0 and Bank 1)
Command Codes
Commands and Command Parameters
64K
(Bank 0)
Data and Mask Addressing
Commands
64K
(Bank 1)
00
01
10
11
(72-bit configuration)
71
Command
65535
65535
Search
72
Learn
Read
Write
0
1
2
3
3
0
1
2
Figure 9-1. Addressing the CYNSE70256 Data and Mask Arrays
0
CFG = 1010101010101010 (Bank 0 and Bank 1)
16K
16K
Writes one of the following: data array, mask array, device registers, or external SRAM.
Reads one of the following: data array, mask array, device registers, or external SRAM.
Searches the data array for a desired pattern using the specified register from the GMR
array and local mask associated with each data cell.
The device has internal storage for up to sixteen comparands that it can learn. The
device controller can insert these entries at the next-free address (as specified by the
NFA register) using the Learn instruction.
(288-bit configuration)
283
65532
65532
72
0
4
0
4
65533
65533
72
1
5
1
5
65534
65534
72
2
6
2
6
65535
65535
72
CFG = 0101010101010101 (Bank 0 and Bank 1)
3
7
3
7
Description
0
32K
32K
(144-bit configuration)
143
65534 65535
65534
72
0
2
4
6
0
2
4
6
65535
72
1
1
3
5
7
3
5
7
0
CYNSE70256
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