CYNSE70256-66BHC Cypress Semiconductor Corp, CYNSE70256-66BHC Datasheet - Page 82

• Manufacturer Part Number: CYNSE70256-66BHC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70256-66BHC

• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

10.6.8
This subsection will cover the mixed-size searches (×72, ×144 and ×288) with tables of different widths (×72, ×144, ×288) with
CFG_L set HIGH. The previous subsection described searches on tables of different widths using table designation bits in the
data array, which can be wasteful. In order to avoid the waste of these bits and yet support up to three tables of ×72, ×144 and
×288 widths, CMD[2] and CMD[9] (in CFG_L HIGH mode) in cycle A of the command can be used as shown in Table 10-28.
Table 10-28. Searches with CFG_L Set HIGH
10.7
When NSEs are cascaded using multiple CYNSE70256 devices, the SADR, CE_L, and WE_L (three-state signals) are all tied
together. In order to eliminate external pull-up and pull downs, one device in a bank is designated the default driver. For nonSearch
or nonLearn cycles (see Subsection 10.8, “Learn Command”) or Search cycles with a global miss, the SADR, CE_L, and WE_L
signals are driven by the device with the LRAM bit set. It is important that only one device in a bank of cascaded NSEs have this
bit set. Failure to do so will cause contention on the SADR, CE_L, and WE_L, and can potentially cause damage to the device(s).
Similarly, when NSEs using multiple CYNSE70256 devices are cascaded, SSF and SSV (also three-state signals) are tied
together. In order to eliminate external pull-up and pull downs, one device in a bank is designated as the default driver. For
nonSearch cycles or Search cycles with a global miss, the SSF and SSV signals are driven by the device with the LDEV bit set
in Bank 1. It is important that only one device in a bank of cascaded NSEs have this bit set. Failure to do so will cause contention
on the SSV and SSF, and can potentially cause damage to the device(s).
10.8
Bit[0] of each 72-bit data location specifies whether an entry in the database is occupied. If all the entries in a device are occupied,
the device asserts a FULO signal to inform the downstream devices that it is full. The result of this communication between depth-
cascaded devices determines the global FULL signal for the entire table. The FULL signal in the last device determines the
fullness of the depth-cascaded table.
The device contains sixteen pairs of internal 72-bit-wide comparand registers that store the comparands as the device executes
searches. On a miss by the Search that is signalled to the ASIC through the SSV and SSF signals (SSV = 1, SSF = 0), the host
ASIC can apply the Learn command to learn the entry from a comparand register as to the next-free location (see Subsection 7.8,
“NFA Register,” on page 17).
The NFA register is updated with the new next-free location information following each Write or Learn command. In a depth-
cascaded table, only a single device will Learn the entry through the application of a Learn instruction. The determination as to
which device will Learn is based on the FULI and FULO signals between the devices. The first non-full device learns the entry
by storing the contents of the specified comparand registers to the location(s) pointed to by the NFA register. In a ×72-configured
table, the Learn command writes a single 72-bit location. In a ×144-configured table, the Learn command writes the next even
and odd 72-bit locations. In 144-bit mode, bit[0] of the even and odd 72-bit locations is 0, indicating that they are cascaded empty,
or 1, indicating that they are occupied. The global FULL signal indicates to the table controller (the host ASIC) that all entries
within a block are occupied and that no more entries can be learned. The CYNSE70256 device updates the signal after each
Write or Learn command to a data array. The Learn command generates a Write cycle to the external SRAM, also using the NFA
register as part of the SRAM address (see Section 12.0, “SRAM Addressing,” on page 86).
The Learn command is supported on a single block containing up to four devices if the table is configured either as ×72 or ×144;
it is not supported for ×288-configured tables. The Learn command is a pipelined operation and lasts for two CLK cycles, as
shown in Figure 10-64 and Figure 10-65 where TLSZ = 01. Figure 10-64 and Figure 10-65 assume that the device performing
the Learn operation is not the last device in the table and will therefore have its LRAM bit set to 0.
Note:
Document #: 38-02035 Rev. *E
29. The OE_L for the device with the LRAM bit set goes HIGH for two cycles for each Learn (one during the SRAM Write cycle and one during the cycle before).
The SRAM Write cycle latency from the second cycle of the instruction is shown in Table 10-29.
Mixed-size Searches on Tables Configured to Different Widths using a CYNSE70256 Device with CFG_L HIGH
LRAM and LDEV Description
Learn Command
CMD[9]
X
X
0
1
CMD[2]
0
0
1
0
Search 72-bit-configured partitions only.
Search 144-bit-configured partitions only.
Cycles A and B for searching 288-bit-configured partitions.
Cycles C and D for searching 288-bit-configured partitions.
Search
[29]
CYNSE70256
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